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[Description]: 

Fixed one bug in PciBus. PciBus doesn't clear the bridges bus number for all the root bridges before scanning any of them.
[Impaction]:
 Pci Bus driver.
[Reference Info]:
 EDK tracker 997. 



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@4851 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
vanjeff 2008-03-14 05:58:31 +00:00
parent f0a83bb308
commit 4beb4afe33
2 changed files with 62 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c
View File

@ -237,6 +237,8 @@ Returns:
pConfiguration pConfiguration
); );
gBS->FreePool (pConfiguration);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }

51
IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.c
View File

@ -4,7 +4,7 @@
It abstracts some functions that can be different It abstracts some functions that can be different
between light PCI bus driver and full PCI bus driver between light PCI bus driver and full PCI bus driver
Copyright (c) 2006, Intel Corporation Copyright (c) 2006 - 2008, Intel Corporation
All rights reserved. This program and the accompanying materials All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -1860,9 +1860,15 @@ Returns:
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
UINT16 MinBus; UINT16 MinBus;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors; EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *pConfiguration;
UINT8 StartBusNumber;
LIST_ENTRY RootBridgeList;
LIST_ENTRY *Link;
InitializeHotPlugSupport (); InitializeHotPlugSupport ();
InitializeListHead (&RootBridgeList);
// //
// Notify the bus allocation phase is about to start // Notify the bus allocation phase is about to start
// //
@ -1891,7 +1897,11 @@ Returns:
RootBridgeDev RootBridgeDev
); );
DestroyRootBridge (RootBridgeDev); if (gPciHotPlugInit != NULL) {
InsertTailList (&RootBridgeList, &(RootBridgeDev->Link));
} else {
DestroyRootBridge (RootBridgeDev);
}
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
return Status; return Status;
} }
@ -1906,8 +1916,43 @@ Returns:
if (gPciHotPlugInit != NULL) { if (gPciHotPlugInit != NULL) {
// //
// Wait for all HPC initialized // Reset all assigned PCI bus number in all PPB
// //
RootBridgeHandle = NULL;
Link = GetFirstNode (&RootBridgeList);
while ((PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle) == EFI_SUCCESS) &&
(!IsNull (&RootBridgeList, Link))) {
RootBridgeDev = PCI_IO_DEVICE_FROM_LINK (Link);
//
// Get the Bus information
//
Status = PciResAlloc->StartBusEnumeration (
PciResAlloc,
RootBridgeHandle,
(VOID **) &pConfiguration
);
if (EFI_ERROR (Status)) {
return Status;
}
//
// Get the bus number to start with
//
StartBusNumber = (UINT8) (pConfiguration->AddrRangeMin);
ResetAllPpbBusNumber (
RootBridgeDev,
StartBusNumber
);
gBS->FreePool (pConfiguration);
Link = GetNextNode (&RootBridgeList, Link);
DestroyRootBridge (RootBridgeDev);
}
//
// Wait for all HPC initialized
//
Status = AllRootHPCInitialized (STALL_1_SECOND * 15); Status = AllRootHPCInitialized (STALL_1_SECOND * 15);
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {