mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/SmmCpuFeaturesLib: replace hard-coded machine code
Replace hard-coded machine code with equivalent assembly source code. Changes tested by checking for machine code equivalence by disassembling the original and changed code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chris Ruffin <chris.ruffin@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Chris Ruffin
Eric Dong
parent
94744aa2ce
commit
4c34a8ea19
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@ -1,5 +1,5 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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@ -51,6 +51,11 @@ global ASM_PFX(gStmSmbase)
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global ASM_PFX(gStmXdSupported)
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extern ASM_PFX(gStmSmiHandlerIdtr)
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ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
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ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
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ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
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ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1
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SECTION .text
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BITS 16
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@ -66,8 +71,8 @@ _StmSmiEntryPoint:
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o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
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mov ax, PROTECT_MODE_CS
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mov [cs:bx-0x2],ax
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DB 0x66, 0xbf ; mov edi, SMBASE
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ASM_PFX(gStmSmbase): DD 0
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o32 mov edi, strict dword 0
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StmSmbasePatch:
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lea eax, [edi + (@32bit - _StmSmiEntryPoint) + 0x8000]
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mov [cs:bx-0x6],eax
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mov ebx, cr0
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@ -87,15 +92,15 @@ o16 mov es, ax
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o16 mov fs, ax
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o16 mov gs, ax
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o16 mov ss, ax
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DB 0xbc ; mov esp, imm32
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ASM_PFX(gStmSmiStack): DD 0
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mov esp, strict dword 0
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StmSmiStackPatch:
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mov eax, ASM_PFX(gStmSmiHandlerIdtr)
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lidt [eax]
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jmp ProtFlatMode
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ProtFlatMode:
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DB 0xb8 ; mov eax, imm32
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ASM_PFX(gStmSmiCr3): DD 0
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mov eax, strict dword 0
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StmSmiCr3Patch:
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mov cr3, eax
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;
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; Need to test for CR4 specific bit support
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@ -134,8 +139,8 @@ ASM_PFX(gStmSmiCr3): DD 0
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.6:
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; enable NXE if supported
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DB 0b0h ; mov al, imm8
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ASM_PFX(gStmXdSupported): DB 1
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mov al, strict byte 1
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StmXdSupportedPatch:
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cmp al, 0
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jz @SkipXd
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;
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@ -268,4 +273,3 @@ _StmSmiHandler:
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ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
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ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint
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@ -1,5 +1,5 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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@ -87,7 +87,7 @@ ASM_PFX(OnException):
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mov ebx, eax
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mov eax, 4
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DB 0x0f, 0x01, 0x0c1 ; VMCALL
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vmcall
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jmp $
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global ASM_PFX(OnStmSetup)
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@ -173,4 +173,3 @@ ASM_PFX(OnStmTeardown):
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.72:
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rsm
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@ -1,5 +1,5 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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@ -61,6 +61,11 @@ global ASM_PFX(gcStmSmiHandlerTemplate)
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global ASM_PFX(gcStmSmiHandlerSize)
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global ASM_PFX(gcStmSmiHandlerOffset)
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ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
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ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
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ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
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ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1
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DEFAULT REL
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SECTION .text
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@ -76,8 +81,8 @@ _StmSmiEntryPoint:
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o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
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mov ax, PROTECT_MODE_CS
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mov [cs:bx-0x2],ax
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DB 0x66, 0xbf ; mov edi, SMBASE
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ASM_PFX(gStmSmbase): DD 0
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o32 mov edi, strict dword 0
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StmSmbasePatch:
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lea eax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 0x8000]
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mov [cs:bx-0x6],eax
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mov ebx, cr0
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@ -97,14 +102,14 @@ o16 mov es, ax
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o16 mov fs, ax
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o16 mov gs, ax
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o16 mov ss, ax
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DB 0xbc ; mov esp, imm32
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ASM_PFX(gStmSmiStack): DD 0
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mov esp, strict dword 0
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StmSmiStackPatch:
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jmp ProtFlatMode
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BITS 64
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ProtFlatMode:
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DB 0xb8 ; mov eax, offset gStmSmiCr3
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ASM_PFX(gStmSmiCr3): DD 0
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mov eax, strict dword 0
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StmSmiCr3Patch:
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mov cr3, rax
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mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3
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mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
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@ -119,8 +124,8 @@ ASM_PFX(gStmSmiCr3): DD 0
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ltr ax
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; enable NXE if supported
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DB 0xb0 ; mov al, imm8
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ASM_PFX(gStmXdSupported): DB 1
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mov al, strict byte 1
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StmXdSupportedPatch:
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cmp al, 0
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jz @SkipXd
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;
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@ -178,8 +183,7 @@ CommonHandler:
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; Save FP registers
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;
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sub rsp, 0x200
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DB 0x48 ; FXSAVE64
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fxsave [rsp]
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fxsave64 [rsp]
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add rsp, -0x20
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@ -200,8 +204,7 @@ CommonHandler:
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;
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; Restore FP registers
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;
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DB 0x48 ; FXRSTOR64
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fxrstor [rsp]
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fxrstor64 [rsp]
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add rsp, 0x200
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@ -1,5 +1,5 @@
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;------------------------------------------------------------------------------ ;
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; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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@ -86,7 +86,7 @@ ASM_PFX(OnException):
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add rsp, 0x28
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mov ebx, eax
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mov eax, 4
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DB 0x0f, 0x01, 0x0c1 ; VMCALL
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vmcall
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jmp $
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global ASM_PFX(OnStmSetup)
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@ -176,4 +176,3 @@ ASM_PFX(OnStmTeardown):
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.12:
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rsm
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