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IntelFsp2Pkg: Adopt FSP 2.3 specification.
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3674 Add ExtendedImageRevision in FSP_INFO_HEADER structure, also add FSP_NON_VOLATILE_STORAGE_HOB2 header. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
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@ -2,7 +2,7 @@
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Intel FSP Header File definition from Intel Firmware Support Package External
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Architecture Specification v2.0 and above.
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Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -44,14 +44,28 @@ typedef struct {
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UINT8 Reserved1[2];
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///
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/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
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/// For revision v2.3 the value will be 0x23.
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///
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UINT8 SpecVersion;
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///
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/// Byte 0x0B: Revision of the FSP Information Header.
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/// The Current value for this field is 0x6.
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///
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UINT8 HeaderRevision;
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///
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/// Byte 0x0C: Revision of the FSP binary.
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/// Major.Minor.Revision.Build
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/// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:
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/// 7 : 0 - Build Number
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/// 15 : 8 - Revision
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/// 23 : 16 - Minor Version
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/// 31 : 24 - Major Version
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/// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision
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/// while ExtendedImageRevision specifies the high-order bytes of the build number and revision.
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/// 7 : 0 - Low Byte of Build Number
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/// 15 : 8 - Low Byte of Revision
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/// 23 : 16 - Minor Version
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/// 31 : 24 - Major Version
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///
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UINT32 ImageRevision;
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///
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@ -116,6 +130,23 @@ typedef struct {
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/// If the value is set to 0x00000000, then this API is not available in this component.
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///
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UINT32 FspMultiPhaseSiInitEntryOffset;
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///
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/// Byte 0x4C: Extended revision of the FSP binary.
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/// This value is only valid if FSP HeaderRevision is >= 6.
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/// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.
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/// 7 : 0 - High Byte of Build Number
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/// 15 : 8 - High Byte of Revision
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/// The FSP binary build number can be decoded as follows:
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/// Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]
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/// Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]
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/// Minor Version = ImageRevision[23:16]
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/// Major Version = ImageRevision[31:24]
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///
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UINT16 ExtendedImageRevision;
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///
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/// Byte 0x4E: Reserved4.
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///
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UINT16 Reserved4;
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} FSP_INFO_HEADER;
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///
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@ -0,0 +1,24 @@
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/** @file
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Intel FSP Non-Volatile Storage (NVS) HOB version 2 definition from
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Intel Firmware Support Package External Architecture Specification v2.3.
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Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef __FSP_NON_VOLATILE_STORAGE_HOB2_H__
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#define __FSP_NON_VOLATILE_STORAGE_HOB2_H__
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///
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/// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support.
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///
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typedef struct {
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EFI_HOB_GUID_TYPE GuidHob;
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EFI_PHYSICAL_ADDRESS NvsDataPtr;
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UINT64 NvsDataLength;
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} FSP_NON_VOLATILE_STORAGE_HOB2;
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extern EFI_GUID gFspNonVolatileStorageHob2Guid;
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#endif
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@ -68,6 +68,7 @@
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# Guid define in FSP EAS
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gFspHeaderFileGuid = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }
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gFspReservedMemoryResourceHobGuid = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }
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gFspNonVolatileStorageHob2Guid = { 0x4866788f, 0x6ba8, 0x47d8, { 0x83, 0x06, 0xac, 0xf7, 0x7f, 0x55, 0x10, 0x46 } }
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gFspNonVolatileStorageHobGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
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gFspBootLoaderTolumHobGuid = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1
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