mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmLib MMU: add functions to set/clear RO and XN bits on regions
Use the refactored UpdateRegionMapping () to traverse the translation tables, splitting block entries along the way if required, and apply a mask + or on each to set or clear the PXN/UXN/XN or RO bits. For now, the 32-bit ARM versions remain unimplemented. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18587 6f19259b-4bc3-4df7-8a09-765794883524
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@ -661,4 +661,28 @@ ArmUnsetCpuActlrBit (
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IN UINTN Bits
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);
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RETURN_STATUS
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ArmSetMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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);
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RETURN_STATUS
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ArmClearMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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);
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RETURN_STATUS
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ArmSetMemoryRegionReadOnly (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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);
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RETURN_STATUS
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ArmClearMemoryRegionReadOnly (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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);
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#endif // __ARM_LIB__
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@ -512,6 +512,96 @@ SetMemoryAttributes (
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return RETURN_SUCCESS;
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}
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STATIC
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RETURN_STATUS
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SetMemoryRegionAttribute (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length,
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IN UINT64 Attributes,
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IN UINT64 BlockEntryMask
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)
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{
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RETURN_STATUS Status;
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UINT64 *RootTable;
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RootTable = ArmGetTTBR0BaseAddress ();
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Status = UpdateRegionMapping (RootTable, BaseAddress, Length, Attributes, BlockEntryMask);
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if (RETURN_ERROR (Status)) {
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return Status;
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}
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// Invalidate all TLB entries so changes are synced
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ArmInvalidateTlb ();
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return RETURN_SUCCESS;
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}
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RETURN_STATUS
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ArmSetMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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UINT64 Val;
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if (ArmReadCurrentEL () == AARCH64_EL1) {
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Val = TT_PXN_MASK | TT_UXN_MASK;
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} else {
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Val = TT_XN_MASK;
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}
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return SetMemoryRegionAttribute (
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BaseAddress,
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Length,
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Val,
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~TT_ADDRESS_MASK_BLOCK_ENTRY);
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}
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RETURN_STATUS
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ArmClearMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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UINT64 Mask;
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// XN maps to UXN in the EL1&0 translation regime
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Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);
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return SetMemoryRegionAttribute (
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BaseAddress,
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Length,
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0,
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Mask);
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}
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RETURN_STATUS
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ArmSetMemoryRegionReadOnly (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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return SetMemoryRegionAttribute (
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BaseAddress,
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Length,
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TT_AP_RO_RO,
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~TT_ADDRESS_MASK_BLOCK_ENTRY);
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}
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RETURN_STATUS
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ArmClearMemoryRegionReadOnly (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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return SetMemoryRegionAttribute (
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BaseAddress,
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Length,
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TT_AP_NO_RO,
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~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));
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}
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RETURN_STATUS
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EFIAPI
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ArmConfigureMmu (
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@ -301,3 +301,39 @@ ArmConfigureMmu (
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ArmEnableMmu();
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return RETURN_SUCCESS;
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}
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RETURN_STATUS
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ArmSetMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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return RETURN_UNSUPPORTED;
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}
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RETURN_STATUS
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ArmClearMemoryRegionNoExec (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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return RETURN_UNSUPPORTED;
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}
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RETURN_STATUS
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ArmSetMemoryRegionReadOnly (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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return RETURN_UNSUPPORTED;
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}
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RETURN_STATUS
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ArmClearMemoryRegionReadOnly (
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IN EFI_PHYSICAL_ADDRESS BaseAddress,
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IN UINT64 Length
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)
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{
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return RETURN_UNSUPPORTED;
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}
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