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ArmPkg/ArmGic: Disentangle v2 and v3 versions of IRQ en/disable APIs
ArmGicLib is agnostic about the difference between v2 and v3, but its APIs are only called from code that is either v2-specific or v3-specific. That makes the generic interface kind of pointless, and we can just merge this code into the callers. Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel
mergify[bot]
parent
a4928a0cfc
commit
4e874fcf09
@ -13,97 +13,6 @@
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#include <Library/IoLib.h>
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#include <Library/PcdLib.h>
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// In GICv3, there are 2 x 64KB frames:
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// Redistributor control frame + SGI Control & Generation frame
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#define GIC_V3_REDISTRIBUTOR_GRANULARITY (ARM_GICR_CTLR_FRAME_SIZE \
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+ ARM_GICR_SGI_PPI_FRAME_SIZE)
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// In GICv4, there are 2 additional 64KB frames:
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// VLPI frame + Reserved page frame
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#define GIC_V4_REDISTRIBUTOR_GRANULARITY (GIC_V3_REDISTRIBUTOR_GRANULARITY \
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+ ARM_GICR_SGI_VLPI_FRAME_SIZE \
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+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
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#define ISENABLER_ADDRESS(base, offset) ((base) +\
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
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#define ICENABLER_ADDRESS(base, offset) ((base) +\
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
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#define IPRIORITY_ADDRESS(base, offset) ((base) +\
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
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/**
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*
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* Return whether the Source interrupt index refers to a shared interrupt (SPI)
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*/
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STATIC
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BOOLEAN
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SourceIsSpi (
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IN UINTN Source
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)
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{
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return Source >= 32 && Source < 1020;
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}
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/**
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* Return the base address of the GIC redistributor for the current CPU
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*
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* @param Revision GIC Revision. The GIC redistributor might have a different
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* granularity following the GIC revision.
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*
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* @retval Base address of the associated GIC Redistributor
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*/
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STATIC
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UINTN
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GicGetCpuRedistributorBase (
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IN UINTN GicRedistributorBase,
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IN ARM_GIC_ARCH_REVISION Revision
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)
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{
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UINTN MpId;
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UINTN CpuAffinity;
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UINTN Affinity;
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UINTN GicCpuRedistributorBase;
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UINT64 TypeRegister;
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MpId = ArmReadMpidr ();
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// Define CPU affinity as:
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// Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32]
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// whereas Affinity3 is defined at [32:39] in MPIDR
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CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) |
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((MpId & ARM_CORE_AFF3) >> 8);
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if (Revision < ARM_GIC_ARCH_REVISION_3) {
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ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
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return 0;
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}
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GicCpuRedistributorBase = GicRedistributorBase;
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do {
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TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
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Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
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if (Affinity == CpuAffinity) {
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return GicCpuRedistributorBase;
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}
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// Move to the next GIC Redistributor frame.
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// The GIC specification does not forbid a mixture of redistributors
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// with or without support for virtual LPIs, so we test Virtual LPIs
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// Support (VLPIS) bit for each frame to decide the granularity.
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// Note: The assumption here is that the redistributors are adjacent
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// for all CPUs. However this may not be the case for NUMA systems.
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GicCpuRedistributorBase += (((ARM_GICR_TYPER_VLPIS & TypeRegister) != 0)
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? GIC_V4_REDISTRIBUTOR_GRANULARITY
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: GIC_V3_REDISTRIBUTOR_GRANULARITY);
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} while ((TypeRegister & ARM_GICR_TYPER_LAST) == 0);
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// The Redistributor has not been found for the current CPU
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ASSERT_EFI_ERROR (EFI_NOT_FOUND);
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return 0;
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}
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/**
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Return the GIC CPU Interrupt Interface ID.
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@ -137,180 +46,6 @@ ArmGicGetMaxNumInterrupts (
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return (ItLines == 0x1f) ? 1020 : 32 * (ItLines + 1);
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}
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VOID
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EFIAPI
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ArmGicSetInterruptPriority (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source,
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IN UINT32 Priority
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)
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{
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UINT32 RegOffset;
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UINT8 RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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// Calculate register offset and bit position
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RegOffset = (UINT32)(Source / 4);
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RegShift = (UINT8)((Source % 4) * 8);
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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SourceIsSpi (Source))
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{
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MmioAndThenOr32 (
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GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
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~(0xff << RegShift),
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Priority << RegShift
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);
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} else {
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GicCpuRedistributorBase = GicGetCpuRedistributorBase (
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GicRedistributorBase,
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Revision
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);
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if (GicCpuRedistributorBase == 0) {
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return;
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}
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MmioAndThenOr32 (
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IPRIORITY_ADDRESS (GicCpuRedistributorBase, RegOffset),
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~(0xff << RegShift),
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Priority << RegShift
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);
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}
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}
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VOID
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EFIAPI
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ArmGicEnableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINT8 RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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// Calculate enable register offset and bit position
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RegOffset = (UINT32)(Source / 32);
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RegShift = (UINT8)(Source % 32);
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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SourceIsSpi (Source))
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{
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// Write set-enable register
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MmioWrite32 (
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GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
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1 << RegShift
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);
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} else {
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GicCpuRedistributorBase = GicGetCpuRedistributorBase (
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GicRedistributorBase,
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Revision
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);
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if (GicCpuRedistributorBase == 0) {
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ASSERT_EFI_ERROR (EFI_NOT_FOUND);
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return;
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}
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// Write set-enable register
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MmioWrite32 (
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ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
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1 << RegShift
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);
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}
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}
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VOID
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EFIAPI
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ArmGicDisableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINT8 RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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// Calculate enable register offset and bit position
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RegOffset = (UINT32)(Source / 32);
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RegShift = (UINT8)(Source % 32);
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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SourceIsSpi (Source))
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{
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// Write clear-enable register
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MmioWrite32 (
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GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
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1 << RegShift
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);
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} else {
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GicCpuRedistributorBase = GicGetCpuRedistributorBase (
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GicRedistributorBase,
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Revision
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);
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if (GicCpuRedistributorBase == 0) {
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return;
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}
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// Write clear-enable register
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MmioWrite32 (
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ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
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1 << RegShift
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);
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}
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}
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BOOLEAN
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EFIAPI
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ArmGicIsInterruptEnabled (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINT8 RegShift;
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ARM_GIC_ARCH_REVISION Revision;
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UINTN GicCpuRedistributorBase;
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UINT32 Interrupts;
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// Calculate enable register offset and bit position
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RegOffset = (UINT32)(Source / 32);
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RegShift = (UINT8)(Source % 32);
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Revision = ArmGicGetSupportedArchRevision ();
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if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
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SourceIsSpi (Source))
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{
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Interrupts = MmioRead32 (
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GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
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);
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} else {
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GicCpuRedistributorBase = GicGetCpuRedistributorBase (
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GicRedistributorBase,
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Revision
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);
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if (GicCpuRedistributorBase == 0) {
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return 0;
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}
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// Read set-enable register
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Interrupts = MmioRead32 (
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ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset)
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);
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}
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return ((Interrupts & (1 << RegShift)) != 0);
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}
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VOID
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EFIAPI
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ArmGicDisableDistributor (
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@ -28,6 +28,73 @@ extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
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STATIC UINTN mGicInterruptInterfaceBase;
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STATIC UINTN mGicDistributorBase;
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STATIC
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VOID
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ArmGicEnableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINT8 RegShift;
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// Calculate enable register offset and bit position
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RegOffset = (UINT32)(Source / 32);
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RegShift = (UINT8)(Source % 32);
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// Write set-enable register
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MmioWrite32 (
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GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
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1 << RegShift
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);
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}
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STATIC
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VOID
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ArmGicDisableInterrupt (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINT8 RegShift;
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// Calculate enable register offset and bit position
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RegOffset = (UINT32)(Source / 32);
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RegShift = (UINT8)(Source % 32);
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// Write clear-enable register
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MmioWrite32 (
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GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
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1 << RegShift
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);
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}
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STATIC
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BOOLEAN
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ArmGicIsInterruptEnabled (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
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IN UINTN Source
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)
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{
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UINT32 RegOffset;
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UINT8 RegShift;
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UINT32 Interrupts;
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// Calculate enable register offset and bit position
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RegOffset = (UINT32)(Source / 32);
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RegShift = (UINT8)(Source % 32);
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Interrupts = MmioRead32 (
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GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
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);
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return ((Interrupts & (1 << RegShift)) != 0);
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}
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/**
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Enable interrupt source Source.
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@ -1,35 +0,0 @@
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/** @file
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*
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* Copyright (c) 2011-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-2-Clause-Patent
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*
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**/
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#include <Library/ArmGicLib.h>
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VOID
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EFIAPI
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ArmGicV2EnableInterruptInterface (
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IN UINTN GicInterruptInterfaceBase
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)
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{
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/*
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* Enable the CPU interface in Non-Secure world
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* Note: The ICCICR register is banked when Security extensions are implemented
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*/
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
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}
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VOID
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EFIAPI
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ArmGicV2DisableInterruptInterface (
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IN UINTN GicInterruptInterfaceBase
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)
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{
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// Disable Gic Interface
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x0);
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x0);
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}
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@ -12,12 +12,248 @@
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#define ARM_GIC_DEFAULT_PRIORITY 0x80
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// In GICv3, there are 2 x 64KB frames:
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// Redistributor control frame + SGI Control & Generation frame
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#define GIC_V3_REDISTRIBUTOR_GRANULARITY (ARM_GICR_CTLR_FRAME_SIZE \
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+ ARM_GICR_SGI_PPI_FRAME_SIZE)
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// In GICv4, there are 2 additional 64KB frames:
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// VLPI frame + Reserved page frame
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#define GIC_V4_REDISTRIBUTOR_GRANULARITY (GIC_V3_REDISTRIBUTOR_GRANULARITY \
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+ ARM_GICR_SGI_VLPI_FRAME_SIZE \
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+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
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#define ISENABLER_ADDRESS(base, offset) ((base) +\
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
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#define ICENABLER_ADDRESS(base, offset) ((base) +\
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
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#define IPRIORITY_ADDRESS(base, offset) ((base) +\
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ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
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extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
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extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
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STATIC UINTN mGicDistributorBase;
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STATIC UINTN mGicRedistributorsBase;
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/**
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*
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* Return whether the Source interrupt index refers to a shared interrupt (SPI)
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*/
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STATIC
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BOOLEAN
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SourceIsSpi (
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IN UINTN Source
|
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)
|
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{
|
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return Source >= 32 && Source < 1020;
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}
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|
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/**
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* Return the base address of the GIC redistributor for the current CPU
|
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*
|
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* @retval Base address of the associated GIC Redistributor
|
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*/
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STATIC
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UINTN
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GicGetCpuRedistributorBase (
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IN UINTN GicRedistributorBase
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)
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{
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UINTN MpId;
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UINTN CpuAffinity;
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UINTN Affinity;
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UINTN GicCpuRedistributorBase;
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UINT64 TypeRegister;
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MpId = ArmReadMpidr ();
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// Define CPU affinity as:
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// Affinity0[0:8], Affinity1[9:15], Affinity2[16:23], Affinity3[24:32]
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// whereas Affinity3 is defined at [32:39] in MPIDR
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CpuAffinity = (MpId & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) |
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((MpId & ARM_CORE_AFF3) >> 8);
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GicCpuRedistributorBase = GicRedistributorBase;
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do {
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TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
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Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
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if (Affinity == CpuAffinity) {
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return GicCpuRedistributorBase;
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}
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// Move to the next GIC Redistributor frame.
|
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// The GIC specification does not forbid a mixture of redistributors
|
||||
// with or without support for virtual LPIs, so we test Virtual LPIs
|
||||
// Support (VLPIS) bit for each frame to decide the granularity.
|
||||
// Note: The assumption here is that the redistributors are adjacent
|
||||
// for all CPUs. However this may not be the case for NUMA systems.
|
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GicCpuRedistributorBase += (((ARM_GICR_TYPER_VLPIS & TypeRegister) != 0)
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? GIC_V4_REDISTRIBUTOR_GRANULARITY
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: GIC_V3_REDISTRIBUTOR_GRANULARITY);
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} while ((TypeRegister & ARM_GICR_TYPER_LAST) == 0);
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// The Redistributor has not been found for the current CPU
|
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ASSERT_EFI_ERROR (EFI_NOT_FOUND);
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return 0;
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}
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STATIC
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VOID
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ArmGicSetInterruptPriority (
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IN UINTN GicDistributorBase,
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IN UINTN GicRedistributorBase,
|
||||
IN UINTN Source,
|
||||
IN UINT32 Priority
|
||||
)
|
||||
{
|
||||
UINT32 RegOffset;
|
||||
UINT8 RegShift;
|
||||
UINTN GicCpuRedistributorBase;
|
||||
|
||||
// Calculate register offset and bit position
|
||||
RegOffset = (UINT32)(Source / 4);
|
||||
RegShift = (UINT8)((Source % 4) * 8);
|
||||
|
||||
if (SourceIsSpi (Source)) {
|
||||
MmioAndThenOr32 (
|
||||
GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
|
||||
~(0xff << RegShift),
|
||||
Priority << RegShift
|
||||
);
|
||||
} else {
|
||||
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
|
||||
GicRedistributorBase
|
||||
);
|
||||
if (GicCpuRedistributorBase == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
MmioAndThenOr32 (
|
||||
IPRIORITY_ADDRESS (GicCpuRedistributorBase, RegOffset),
|
||||
~(0xff << RegShift),
|
||||
Priority << RegShift
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
STATIC
|
||||
VOID
|
||||
ArmGicEnableInterrupt (
|
||||
IN UINTN GicDistributorBase,
|
||||
IN UINTN GicRedistributorBase,
|
||||
IN UINTN Source
|
||||
)
|
||||
{
|
||||
UINT32 RegOffset;
|
||||
UINT8 RegShift;
|
||||
UINTN GicCpuRedistributorBase;
|
||||
|
||||
// Calculate enable register offset and bit position
|
||||
RegOffset = (UINT32)(Source / 32);
|
||||
RegShift = (UINT8)(Source % 32);
|
||||
|
||||
if (SourceIsSpi (Source)) {
|
||||
// Write set-enable register
|
||||
MmioWrite32 (
|
||||
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
|
||||
1 << RegShift
|
||||
);
|
||||
} else {
|
||||
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
|
||||
GicRedistributorBase
|
||||
);
|
||||
if (GicCpuRedistributorBase == 0) {
|
||||
ASSERT_EFI_ERROR (EFI_NOT_FOUND);
|
||||
return;
|
||||
}
|
||||
|
||||
// Write set-enable register
|
||||
MmioWrite32 (
|
||||
ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
|
||||
1 << RegShift
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
STATIC
|
||||
VOID
|
||||
ArmGicDisableInterrupt (
|
||||
IN UINTN GicDistributorBase,
|
||||
IN UINTN GicRedistributorBase,
|
||||
IN UINTN Source
|
||||
)
|
||||
{
|
||||
UINT32 RegOffset;
|
||||
UINT8 RegShift;
|
||||
UINTN GicCpuRedistributorBase;
|
||||
|
||||
// Calculate enable register offset and bit position
|
||||
RegOffset = (UINT32)(Source / 32);
|
||||
RegShift = (UINT8)(Source % 32);
|
||||
|
||||
if (SourceIsSpi (Source)) {
|
||||
// Write clear-enable register
|
||||
MmioWrite32 (
|
||||
GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
|
||||
1 << RegShift
|
||||
);
|
||||
} else {
|
||||
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
|
||||
GicRedistributorBase
|
||||
);
|
||||
if (GicCpuRedistributorBase == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
// Write clear-enable register
|
||||
MmioWrite32 (
|
||||
ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
|
||||
1 << RegShift
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
STATIC
|
||||
BOOLEAN
|
||||
ArmGicIsInterruptEnabled (
|
||||
IN UINTN GicDistributorBase,
|
||||
IN UINTN GicRedistributorBase,
|
||||
IN UINTN Source
|
||||
)
|
||||
{
|
||||
UINT32 RegOffset;
|
||||
UINT8 RegShift;
|
||||
UINTN GicCpuRedistributorBase;
|
||||
UINT32 Interrupts;
|
||||
|
||||
// Calculate enable register offset and bit position
|
||||
RegOffset = (UINT32)(Source / 32);
|
||||
RegShift = (UINT8)(Source % 32);
|
||||
|
||||
if (SourceIsSpi (Source)) {
|
||||
Interrupts = MmioRead32 (
|
||||
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
|
||||
);
|
||||
} else {
|
||||
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
|
||||
GicRedistributorBase
|
||||
);
|
||||
if (GicCpuRedistributorBase == 0) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Read set-enable register
|
||||
Interrupts = MmioRead32 (
|
||||
ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset)
|
||||
);
|
||||
}
|
||||
|
||||
return ((Interrupts & (1 << RegShift)) != 0);
|
||||
}
|
||||
|
||||
/**
|
||||
Enable interrupt source Source.
|
||||
|
||||
|
||||
@ -158,39 +158,6 @@ ArmGicSetPriorityMask (
|
||||
IN INTN PriorityMask
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmGicSetInterruptPriority (
|
||||
IN UINTN GicDistributorBase,
|
||||
IN UINTN GicRedistributorBase,
|
||||
IN UINTN Source,
|
||||
IN UINT32 Priority
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmGicEnableInterrupt (
|
||||
IN UINTN GicDistributorBase,
|
||||
IN UINTN GicRedistributorBase,
|
||||
IN UINTN Source
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmGicDisableInterrupt (
|
||||
IN UINTN GicDistributorBase,
|
||||
IN UINTN GicRedistributorBase,
|
||||
IN UINTN Source
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
EFIAPI
|
||||
ArmGicIsInterruptEnabled (
|
||||
IN UINTN GicDistributorBase,
|
||||
IN UINTN GicRedistributorBase,
|
||||
IN UINTN Source
|
||||
);
|
||||
|
||||
// GIC revision 2 specific declarations
|
||||
|
||||
// Interrupts from 1020 to 1023 are considered as special interrupts
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user