mirror of https://github.com/acidanthera/audk.git
ArmPkg/PL310L2Cache: Remove magic values in PL310L2Cache and clean the code
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11735 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
63adfb1129
commit
51d191aad5
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@ -15,7 +15,7 @@
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#include <Library/IoLib.h>
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#include <Library/IoLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DebugLib.h>
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#include <Library/ArmLib.h>
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#include <Library/ArmLib.h>
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#include <Library/L2X0CacheLib.h>
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#include <Drivers/PL310L2Cache.h>
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#include <Library/PcdLib.h>
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#include <Library/PcdLib.h>
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#define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)
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#define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)
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@ -25,6 +25,10 @@
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VOID
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VOID
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L2x0CacheInit (
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L2x0CacheInit (
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IN UINTN L2x0Base,
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IN UINTN L2x0Base,
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IN UINT32 L2x0TagLatencies,
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IN UINT32 L2x0DataLatencies,
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IN UINT32 L2x0AuxValue,
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IN UINT32 L2x0AuxMask,
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IN BOOLEAN CacheEnabled
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IN BOOLEAN CacheEnabled
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)
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)
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{
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{
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@ -66,9 +70,9 @@ L2x0CacheInit (
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Aux |= L2x0_AUXCTRL_AW_AWCACHE;
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Aux |= L2x0_AUXCTRL_AW_AWCACHE;
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// Use default Size
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// Use default Size
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Data = L2x0ReadReg(L2X0_AUXCTRL);
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Data = L2x0ReadReg(L2X0_AUXCTRL);
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Aux |= Data & (0x7 << 17);
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Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK;
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// Use default associativity
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// Use default associativity
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Aux |= Data & (0x1 << 16);
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Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY;
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// Enabled I & D Prefetch
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// Enabled I & D Prefetch
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Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;
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Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;
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@ -88,29 +92,16 @@ L2x0CacheInit (
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L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);
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L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);
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}
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}
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if (Revision >= 4) {
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if (Revision >= 2) {
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// Tag RAM Latency register
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L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies);
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// - Use default latency
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L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies);
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} else {
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// PL310 old style latency is not supported yet
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ASSERT(0);
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}
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// Data RAM Latency Control register
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// Set the platform specific values
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// - Use default latency
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Aux = (Aux & L2x0AuxMask) | L2x0AuxValue;
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} else if (Revision >= 2) {
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L2x0WriteReg(L230_TAG_LATENCY,
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(L2_TAG_ACCESS_LATENCY << 8)
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| (L2_TAG_ACCESS_LATENCY << 4)
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| L2_TAG_SETUP_LATENCY
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);
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L2x0WriteReg(L230_DATA_LATENCY,
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(L2_DATA_ACCESS_LATENCY << 8)
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| (L2_DATA_ACCESS_LATENCY << 4)
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| L2_DATA_SETUP_LATENCY
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);
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} else {
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Aux |= (L2_TAG_ACCESS_LATENCY << 6)
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| (L2_DATA_ACCESS_LATENCY << 3)
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| L2_DATA_ACCESS_LATENCY;
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}
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// Write Auxiliary value
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// Write Auxiliary value
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L2x0WriteReg(L2X0_AUXCTRL, Aux);
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L2x0WriteReg(L2X0_AUXCTRL, Aux);
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@ -0,0 +1,79 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef L2CACHELIB_H_
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#define L2CACHELIB_H_
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#define L2X0_CACHEID 0x000
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#define L2X0_CTRL 0x100
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#define L2X0_AUXCTRL 0x104
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#define L230_TAG_LATENCY 0x108
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#define L230_DATA_LATENCY 0x10C
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#define L2X0_INTCLEAR 0x220
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#define L2X0_CACHE_SYNC 0x730
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#define L2X0_INVWAY 0x77C
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#define L2X0_CLEAN_WAY 0x7BC
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#define L2X0_PFCTRL 0xF60
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#define L2X0_PWRCTRL 0xF80
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#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41
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#define L2X0_CACHEID_PARTNUM_PL310 0x03
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#define L2X0_CTRL_ENABLED 0x1
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#define L2X0_CTRL_DISABLED 0x0
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#define L2X0_AUXCTRL_EXCLUSIVE (1 << 12)
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#define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16)
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#define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17)
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#define L2X0_AUXCTRL_EM (1 << 20)
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#define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22)
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#define L2x0_AUXCTRL_AW_AWCACHE (0 << 23)
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#define L2x0_AUXCTRL_AW_NOALLOC (1 << 23)
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#define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23)
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#define L2X0_AUXCTRL_SBO (1 << 25)
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#define L2X0_AUXCTRL_NSAC (1 << 27)
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#define L2x0_AUXCTRL_DPREFETCH (1 << 28)
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#define L2x0_AUXCTRL_IPREFETCH (1 << 29)
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#define L2x0_AUXCTRL_EARLY_BRESP (1 << 30)
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#define L2x0_LATENCY_1_CYCLE 0
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#define L2x0_LATENCY_2_CYCLES 1
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#define L2x0_LATENCY_3_CYCLES 2
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#define L2x0_LATENCY_4_CYCLES 3
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#define L2x0_LATENCY_5_CYCLES 4
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#define L2x0_LATENCY_6_CYCLES 5
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#define L2x0_LATENCY_7_CYCLES 6
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#define L2x0_LATENCY_8_CYCLES 7
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#define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup))
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#define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)
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#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup)
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VOID
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L2x0CacheInit (
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IN UINTN L2x0Base,
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IN UINT32 L2x0TagLatencies,
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IN UINT32 L2x0DataLatencies,
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IN UINT32 L2x0AuxValue,
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IN UINT32 L2x0AuxMask,
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IN BOOLEAN CacheEnabled
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);
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#endif /* L2CACHELIB_H_ */
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@ -1,62 +0,0 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef L2CACHELIB_H_
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#define L2CACHELIB_H_
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#define L2_LATENCY 7
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#define L2_TAG_ACCESS_LATENCY L2_LATENCY
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#define L2_TAG_SETUP_LATENCY L2_LATENCY
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#define L2_DATA_ACCESS_LATENCY L2_LATENCY
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#define L2_DATA_SETUP_LATENCY L2_LATENCY
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#define L2X0_CACHEID 0x000
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#define L2X0_CTRL 0x100
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#define L2X0_AUXCTRL 0x104
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#define L230_TAG_LATENCY 0x108
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#define L230_DATA_LATENCY 0x10C
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#define L2X0_INTCLEAR 0x220
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#define L2X0_CACHE_SYNC 0x730
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#define L2X0_INVWAY 0x77C
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#define L2X0_CLEAN_WAY 0x7BC
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#define L2X0_PFCTRL 0xF60
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#define L2X0_PWRCTRL 0xF80
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#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41
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#define L2X0_CACHEID_PARTNUM_PL310 0x03
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#define L2X0_CTRL_ENABLED 0x1
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#define L2X0_CTRL_DISABLED 0x0
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#define L2X0_AUXCTRL_EXCLUSIVE (1<<12)
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#define L2X0_AUXCTRL_WAYSIZE_16KB (0x001 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_32KB (0x010 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_64KB (0x011 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_128KB (0x100 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_256KB (0x101 << 17)
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#define L2X0_AUXCTRL_WAYSIZE_512KB (0x110 << 17)
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#define L2X0_AUXCTRL_EM (1 << 20)
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#define L2x0_AUXCTRL_AW_AWCACHE (0x00 << 23)
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#define L2x0_AUXCTRL_AW_NOALLOC (0x01 << 23)
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#define L2x0_AUXCTRL_AW_OVERRIDE (0x10 << 23)
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#define L2X0_AUXCTRL_SBO (1 << 25)
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#define L2X0_AUXCTRL_NSAC (1 << 27)
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#define L2x0_AUXCTRL_DPREFETCH (1 << 28)
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#define L2x0_AUXCTRL_IPREFETCH (1 << 29)
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VOID L2x0CacheInit(UINTN L2x0Base, BOOLEAN CacheEnabled);
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#endif /* L2CACHELIB_H_ */
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@ -12,12 +12,17 @@
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*
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*
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**/
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**/
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#include <Library/L2X0CacheLib.h>
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#include <Uefi.h>
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#include <Drivers/PL310L2Cache.h>
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// Initialize L2X0 Cache Controller
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// Initialize L2X0 Cache Controller
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VOID
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VOID
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L2x0CacheInit (
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L2x0CacheInit (
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IN UINTN L2x0Base,
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IN UINTN L2x0Base,
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IN UINT32 L2x0TagLatencies,
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IN UINT32 L2x0DataLatencies,
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IN UINT32 L2x0AuxValue,
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IN UINT32 L2x0AuxMask,
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IN BOOLEAN CacheEnabled
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IN BOOLEAN CacheEnabled
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)
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)
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{
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{
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@ -19,7 +19,7 @@
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#include <Library/PcdLib.h>
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#include <Library/PcdLib.h>
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#include <Drivers/PL341Dmc.h>
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#include <Drivers/PL341Dmc.h>
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#include <Drivers/PL301Axi.h>
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#include <Drivers/PL301Axi.h>
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#include <Library/L2X0CacheLib.h>
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#include <Drivers/PL310L2Cache.h>
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#include <Library/SerialPortLib.h>
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#include <Library/SerialPortLib.h>
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#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
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#define SerialPrint(txt) SerialPortWrite (txt, AsciiStrLen(txt)+1);
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@ -186,7 +186,11 @@ ArmPlatformSecInitialize (
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VOID
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VOID
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) {
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) {
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// The L2x0 controller must be intialize in Secure World
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// The L2x0 controller must be intialize in Secure World
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L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase), FALSE);
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L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase),
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PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
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PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
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0,~0, // Use default setting for the Auxiliary Control Register
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FALSE);
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}
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}
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/**
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/**
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