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ArmPlatformPkg/Sec: Removed SetupExceptionLevel3() 

This function only does the GIC initialization that is always taken care by Sec.c.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14581 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2013-08-21 12:07:01 +00:00 committed by oliviermartin
parent cc93554486
commit 5232a5e2af
1 changed files with 0 additions and 44 deletions
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44
ArmPlatformPkg/Sec/AArch64/Helper.S
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@ -18,41 +18,12 @@
.text
.align 3
ASM_GLOBAL ASM_PFX(SetupExceptionLevel3)
ASM_GLOBAL ASM_PFX(SwitchToNSExceptionLevel1)
ASM_GLOBAL ASM_PFX(enter_monitor_mode)
ASM_GLOBAL ASM_PFX(return_from_exception)
ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)
ASM_GLOBAL ASM_PFX(set_non_secure_mode)
ASM_PFX(SetupExceptionLevel3):
// Check for the primary CPU to avoid a race on the distributor registers.
mrs x0, mpidr_el1
tst x0, #15
b.ne 1f // secondary CPU
LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)
mov w0, #3 // EnableGrp0 | EnableGrp1
str w0, [x1]
1: LoadConstantToReg (FixedPcdGet32(PcdGicDistributorBase), x1)
add x1, x1, #0x80
mov w0, #~0 // Grp1 interrupts
str w0, [x1], #4
b.ne 2f // Only local interrupts for secondary CPUs
str w0, [x1], #4
str w0, [x1], #4
2: LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)
ldr w0, [x1]
mov w0, #3 // EnableGrp0 | EnableGrp1
str w0, [x1]
mov w0, #1 << 7 // allow NS access to GICC_PMR
str w0, [x1, #4] // GICC_PMR
ret
// Switch from EL3 to NS-EL1
ASM_PFX(SwitchToNSExceptionLevel1):
// Now setup our EL1. Controlled by EL2 config on Model
@ -104,21 +75,6 @@ ASM_PFX(enter_monitor_mode):
// We may need to do some config before we change to another Mode.
ASM_PFX(return_from_exception):
msr elr_el3, x0
mrs x7, spsr_el3
ands w7, w7, #0xC
cmp w7, #0xC // EL3?
b.eq 3f
bl ASM_PFX(SetupExceptionLevel3)
cmp w7, #0x8 // EL2?
b.eq 2f
cmp w7, #0x4 // EL1?
b.eq 1f
b dead // We should never get here.
1: bl ASM_PFX(SwitchToNSExceptionLevel1)
2: // EL2: No more setup required.
3: // EL3: Not sure why we would do this.
eret
// For AArch64 we need to construct the spsr we want from individual bits and pieces.