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UefiCpuPkg: Add PiSmmCpuDxeSmm module no IA32/X64 files 

Add module that initializes a CPU for the SMM environment and
installs the first level SMI handler.  This module along with the
SMM IPL and SMM Core provide the services required for
DXE_SMM_DRIVERS to register hardware and software SMI handlers.

CPU specific features are abstracted through the SmmCpuFeaturesLib

Platform specific features are abstracted through the
SmmCpuPlatformHookLib

Several PCDs are added to enable/disable features and configure
settings for the PiSmmCpuDxeSmm module

Changes between [PATCH v1] and [PATCH v2]:
1) Swap PTE init order for QEMU compatibility.
   Current PTE initialization algorithm works on HW but breaks QEMU
   emulator.  Update the PTE initialization order to be compatible
   with both.
2) Update comment block that describes 32KB SMBASE alignment requirement
   to match contents of Intel(R) 64 and IA-32 Architectures Software
   Developer's Manual
3) Remove BUGBUG comment and call to ClearSmi() that is not required.
   SMI should be cleared by root SMI handler.

[jeff.fan@intel.com: Fix code style issues reported by ECC]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>

[pbonzini@redhat.com: InitPaging: prepare PT before filling in PDE]
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18645 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney 2015-10-19 19:12:53 +00:00 committed by mdkinney
parent 406c720054
commit 529a5a8609
16 changed files with 7503 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

491
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c Normal file
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/** @file
Code for Processor S3 restoration
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "PiSmmCpuDxeSmm.h"
typedef struct {
UINTN Lock;
VOID *StackStart;
UINTN StackSize;
VOID *ApFunction;
IA32_DESCRIPTOR GdtrProfile;
IA32_DESCRIPTOR IdtrProfile;
UINT32 BufferStart;
UINT32 Cr3;
} MP_CPU_EXCHANGE_INFO;
typedef struct {
UINT8 *RendezvousFunnelAddress;
UINTN PModeEntryOffset;
UINTN FlatJumpOffset;
UINTN Size;
UINTN LModeEntryOffset;
UINTN LongJumpOffset;
} MP_ASSEMBLY_ADDRESS_MAP;
/**
Get starting address and size of the rendezvous entry for APs.
Information for fixing a jump instruction in the code is also returned.
@param AddressMap Output buffer for address map information.
**/
VOID *
EFIAPI
AsmGetAddressMap (
MP_ASSEMBLY_ADDRESS_MAP *AddressMap
);
#define LEGACY_REGION_SIZE (2 * 0x1000)
#define LEGACY_REGION_BASE (0xA0000 - LEGACY_REGION_SIZE)
#define MSR_SPIN_LOCK_INIT_NUM 15
ACPI_CPU_DATA mAcpiCpuData;
UINT32 mNumberToFinish;
MP_CPU_EXCHANGE_INFO *mExchangeInfo;
BOOLEAN mRestoreSmmConfigurationInS3 = FALSE;
VOID *mGdtForAp = NULL;
VOID *mIdtForAp = NULL;
VOID *mMachineCheckHandlerForAp = NULL;
MP_MSR_LOCK *mMsrSpinLocks = NULL;
UINTN mMsrSpinLockCount = MSR_SPIN_LOCK_INIT_NUM;
UINTN mMsrCount = 0;
/**
Get MSR spin lock by MSR index.
@param MsrIndex MSR index value.
@return Pointer to MSR spin lock.
**/
SPIN_LOCK *
GetMsrSpinLockByIndex (
IN UINT32 MsrIndex
)
{
UINTN Index;
for (Index = 0; Index < mMsrCount; Index++) {
if (MsrIndex == mMsrSpinLocks[Index].MsrIndex) {
return &mMsrSpinLocks[Index].SpinLock;
}
}
return NULL;
}
/**
Initialize MSR spin lock by MSR index.
@param MsrIndex MSR index value.
**/
VOID
InitMsrSpinLockByIndex (
IN UINT32 MsrIndex
)
{
UINTN NewMsrSpinLockCount;
if (mMsrSpinLocks == NULL) {
mMsrSpinLocks = (MP_MSR_LOCK *) AllocatePool (sizeof (MP_MSR_LOCK) * mMsrSpinLockCount);
ASSERT (mMsrSpinLocks != NULL);
}
if (GetMsrSpinLockByIndex (MsrIndex) == NULL) {
//
// Initialize spin lock for MSR programming
//
mMsrSpinLocks[mMsrCount].MsrIndex = MsrIndex;
InitializeSpinLock (&mMsrSpinLocks[mMsrCount].SpinLock);
mMsrCount ++;
if (mMsrCount == mMsrSpinLockCount) {
//
// If MSR spin lock buffer is full, enlarge it
//
NewMsrSpinLockCount = mMsrSpinLockCount + MSR_SPIN_LOCK_INIT_NUM;
mMsrSpinLocks = ReallocatePool (
sizeof (MP_MSR_LOCK) * mMsrSpinLockCount,
sizeof (MP_MSR_LOCK) * NewMsrSpinLockCount,
mMsrSpinLocks
);
mMsrSpinLockCount = NewMsrSpinLockCount;
}
}
}
/**
Sync up the MTRR values for all processors.
@param MtrrTable Table holding fixed/variable MTRR values to be loaded.
**/
VOID
EFIAPI
LoadMtrrData (
EFI_PHYSICAL_ADDRESS MtrrTable
)
/*++
Routine Description:
Sync up the MTRR values for all processors.
Arguments:
Returns:
None
--*/
{
MTRR_SETTINGS *MtrrSettings;
MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable;
MtrrSetAllMtrrs (MtrrSettings);
}
/**
Programs registers for the calling processor.
This function programs registers for the calling processor.
@param RegisterTable Pointer to register table of the running processor.
**/
VOID
SetProcessorRegister (
IN CPU_REGISTER_TABLE *RegisterTable
)
{
CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;
UINTN Index;
UINTN Value;
SPIN_LOCK *MsrSpinLock;
//
// Traverse Register Table of this logical processor
//
RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
for (Index = 0; Index < RegisterTable->TableLength; Index++, RegisterTableEntry++) {
//
// Check the type of specified register
//
switch (RegisterTableEntry->RegisterType) {
//
// The specified register is Control Register
//
case ControlRegister:
switch (RegisterTableEntry->Index) {
case 0:
Value = AsmReadCr0 ();
Value = (UINTN) BitFieldWrite64 (
Value,
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
(UINTN) RegisterTableEntry->Value
);
AsmWriteCr0 (Value);
break;
case 2:
Value = AsmReadCr2 ();
Value = (UINTN) BitFieldWrite64 (
Value,
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
(UINTN) RegisterTableEntry->Value
);
AsmWriteCr2 (Value);
break;
case 3:
Value = AsmReadCr3 ();
Value = (UINTN) BitFieldWrite64 (
Value,
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
(UINTN) RegisterTableEntry->Value
);
AsmWriteCr3 (Value);
break;
case 4:
Value = AsmReadCr4 ();
Value = (UINTN) BitFieldWrite64 (
Value,
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
(UINTN) RegisterTableEntry->Value
);
AsmWriteCr4 (Value);
break;
default:
break;
}
break;
//
// The specified register is Model Specific Register
//
case Msr:
//
// If this function is called to restore register setting after INIT signal,
// there is no need to restore MSRs in register table.
//
if (RegisterTableEntry->ValidBitLength >= 64) {
//
// If length is not less than 64 bits, then directly write without reading
//
AsmWriteMsr64 (
RegisterTableEntry->Index,
RegisterTableEntry->Value
);
} else {
//
// Get lock to avoid Package/Core scope MSRs programming issue in parallel execution mode
// to make sure MSR read/write operation is atomic.
//
MsrSpinLock = GetMsrSpinLockByIndex (RegisterTableEntry->Index);
AcquireSpinLock (MsrSpinLock);
//
// Set the bit section according to bit start and length
//
AsmMsrBitFieldWrite64 (
RegisterTableEntry->Index,
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
RegisterTableEntry->Value
);
ReleaseSpinLock (MsrSpinLock);
}
break;
//
// Enable or disable cache
//
case CacheControl:
//
// If value of the entry is 0, then disable cache. Otherwise, enable cache.
//
if (RegisterTableEntry->Value == 0) {
AsmDisableCache ();
} else {
AsmEnableCache ();
}
break;
default:
break;
}
}
}
/**
AP initialization before SMBASE relocation in the S3 boot path.
**/
VOID
EarlyMPRendezvousProcedure (
VOID
)
{
CPU_REGISTER_TABLE *RegisterTableList;
UINT32 InitApicId;
UINTN Index;
LoadMtrrData (mAcpiCpuData.MtrrTable);
//
// Find processor number for this CPU.
//
RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable;
InitApicId = GetInitialApicId ();
for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
if (RegisterTableList[Index].InitialApicId == InitApicId) {
SetProcessorRegister (&RegisterTableList[Index]);
break;
}
}
//
// Count down the number with lock mechanism.
//
InterlockedDecrement (&mNumberToFinish);
}
/**
AP initialization after SMBASE relocation in the S3 boot path.
**/
VOID
MPRendezvousProcedure (
VOID
)
{
CPU_REGISTER_TABLE *RegisterTableList;
UINT32 InitApicId;
UINTN Index;
ProgramVirtualWireMode ();
DisableLvtInterrupts ();
RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable;
InitApicId = GetInitialApicId ();
for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
if (RegisterTableList[Index].InitialApicId == InitApicId) {
SetProcessorRegister (&RegisterTableList[Index]);
break;
}
}
//
// Count down the number with lock mechanism.
//
InterlockedDecrement (&mNumberToFinish);
}
/**
Prepares startup vector for APs.
This function prepares startup vector for APs.
@param WorkingBuffer The address of the work buffer.
**/
VOID
PrepareApStartupVector (
EFI_PHYSICAL_ADDRESS WorkingBuffer
)
{
EFI_PHYSICAL_ADDRESS StartupVector;
MP_ASSEMBLY_ADDRESS_MAP AddressMap;
//
// Get the address map of startup code for AP,
// including code size, and offset of long jump instructions to redirect.
//
ZeroMem (&AddressMap, sizeof (AddressMap));
AsmGetAddressMap (&AddressMap);
StartupVector = WorkingBuffer;
//
// Copy AP startup code to startup vector, and then redirect the long jump
// instructions for mode switching.
//
CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);
*(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset);
if (AddressMap.LongJumpOffset != 0) {
*(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset);
}
//
// Get the start address of exchange data between BSP and AP.
//
mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size);
ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));
CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));
CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));
//
// Copy AP's GDT, IDT and Machine Check handler from SMRAM to ACPI NVS memory
//
CopyMem ((VOID *) mExchangeInfo->GdtrProfile.Base, mGdtForAp, mExchangeInfo->GdtrProfile.Limit + 1);
CopyMem ((VOID *) mExchangeInfo->IdtrProfile.Base, mIdtForAp, mExchangeInfo->IdtrProfile.Limit + 1);
CopyMem ((VOID *)(UINTN) mAcpiCpuData.ApMachineCheckHandlerBase, mMachineCheckHandlerForAp, mAcpiCpuData.ApMachineCheckHandlerSize);
mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;
mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
mExchangeInfo->BufferStart = (UINT32) StartupVector;
mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());
}
/**
The function is invoked before SMBASE relocation in S3 path to restores CPU status.
The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
and restores MTRRs for both BSP and APs.
**/
VOID
EarlyInitializeCpu (
VOID
)
{
CPU_REGISTER_TABLE *RegisterTableList;
UINT32 InitApicId;
UINTN Index;
LoadMtrrData (mAcpiCpuData.MtrrTable);
//
// Find processor number for this CPU.
//
RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmmInitRegisterTable;
InitApicId = GetInitialApicId ();
for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
if (RegisterTableList[Index].InitialApicId == InitApicId) {
SetProcessorRegister (&RegisterTableList[Index]);
break;
}
}
ProgramVirtualWireMode ();
PrepareApStartupVector (mAcpiCpuData.StartupVector);
mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
mExchangeInfo->ApFunction = (VOID *) (UINTN) EarlyMPRendezvousProcedure;
//
// Send INIT IPI - SIPI to all APs
//
SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
while (mNumberToFinish > 0) {
CpuPause ();
}
}
/**
The function is invoked after SMBASE relocation in S3 path to restores CPU status.
The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
data saved by normal boot path for both BSP and APs.
**/
VOID
InitializeCpu (
VOID
)
{
CPU_REGISTER_TABLE *RegisterTableList;
UINT32 InitApicId;
UINTN Index;
RegisterTableList = (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.RegisterTable;
InitApicId = GetInitialApicId ();
for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {
if (RegisterTableList[Index].InitialApicId == InitApicId) {
SetProcessorRegister (&RegisterTableList[Index]);
break;
}
}
mNumberToFinish = mAcpiCpuData.NumberOfCpus - 1;
//
// StackStart was updated when APs were waken up in EarlyInitializeCpu.
// Re-initialize StackAddress to original beginning address.
//
mExchangeInfo->StackStart = (VOID *) (UINTN) mAcpiCpuData.StackAddress;
mExchangeInfo->ApFunction = (VOID *) (UINTN) MPRendezvousProcedure;
//
// Send INIT IPI - SIPI to all APs
//
SendInitSipiSipiAllExcludingSelf ((UINT32)mAcpiCpuData.StartupVector);
while (mNumberToFinish > 0) {
CpuPause ();
}
}

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UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c Normal file
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/** @file
Implementation of SMM CPU Services Protocol.
Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "PiSmmCpuDxeSmm.h"
//
// SMM CPU Service Protocol instance
//
EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService = {
SmmGetProcessorInfo,
SmmSwitchBsp,
SmmAddProcessor,
SmmRemoveProcessor,
SmmWhoAmI,
SmmRegisterExceptionHandler
};
/**
Get Package ID/Core ID/Thread ID of a processor.
APIC ID must be an initial APIC ID.
The algorithm below assumes the target system has symmetry across physical package boundaries
with respect to the number of logical processors per package, number of cores per package.
@param ApicId APIC ID of the target logical processor.
@param Location Returns the processor location information.
**/
VOID
SmmGetProcessorLocation (
IN UINT32 ApicId,
OUT EFI_CPU_PHYSICAL_LOCATION *Location
)
{
UINTN ThreadBits;
UINTN CoreBits;
UINT32 RegEax;
UINT32 RegEbx;
UINT32 RegEcx;
UINT32 RegEdx;
UINT32 MaxCpuIdIndex;
UINT32 SubIndex;
UINTN LevelType;
UINT32 MaxLogicProcessorsPerPackage;
UINT32 MaxCoresPerPackage;
BOOLEAN TopologyLeafSupported;
ASSERT (Location != NULL);
ThreadBits = 0;
CoreBits = 0;
TopologyLeafSupported = FALSE;
//
// Check if the processor is capable of supporting more than one logical processor.
//
AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
ASSERT ((RegEdx & BIT28) != 0);
//
// Assume three-level mapping of APIC ID: Package:Core:SMT.
//
//
// Get the max index of basic CPUID
//
AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
//
// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
// basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
// supported on that processor.
//
if ((RegEbx & 0xffff) != 0) {
TopologyLeafSupported = TRUE;
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
//
LevelType = (RegEcx >> 8) & 0xff;
ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
if ((RegEbx & 0xffff) > 1 ) {
ThreadBits = RegEax & 0x1f;
} else {
//
// HT is not supported
//
ThreadBits = 0;
}
//
// Software must not assume any "level type" encoding
// value to be related to any sub-leaf index, except sub-leaf 0.
//
SubIndex = 1;
do {
AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);
LevelType = (RegEcx >> 8) & 0xff;
if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
CoreBits = (RegEax & 0x1f) - ThreadBits;
break;
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
}
}
if (!TopologyLeafSupported) {
AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
MaxCoresPerPackage = (RegEax >> 26) + 1;
} else {
//
// Must be a single-core processor.
//
MaxCoresPerPackage = 1;
}
ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
}
Location->Thread = ApicId & ~((-1) << ThreadBits);
Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
Location->Package = (ApicId >> (ThreadBits+ CoreBits));
}
/**
Gets processor information on the requested processor at the instant this call is made.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[in] ProcessorNumber The handle number of processor.
@param[out] ProcessorInfoBuffer A pointer to the buffer where information for
the requested processor is deposited.
@retval EFI_SUCCESS Processor information was returned.
@retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
@retval EFI_INVALID_PARAMETER ProcessorNumber is invalid.
@retval EFI_NOT_FOUND The processor with the handle specified by
ProcessorNumber does not exist in the platform.
**/
EFI_STATUS
EFIAPI
SmmGetProcessorInfo (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
)
{
//
// Check parameter
//
if (ProcessorNumber >= mMaxNumberOfCpus || ProcessorInfoBuffer == NULL) {
return EFI_INVALID_PARAMETER;
}
if (gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID) {
return EFI_NOT_FOUND;
}
//
// Fill in processor information
//
CopyMem (ProcessorInfoBuffer, &gSmmCpuPrivate->ProcessorInfo[ProcessorNumber], sizeof (EFI_PROCESSOR_INFORMATION));
return EFI_SUCCESS;
}
/**
This service switches the requested AP to be the BSP since the next SMI.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[in] ProcessorNumber The handle number of AP that is to become the new BSP.
@retval EFI_SUCCESS BSP will be switched in next SMI.
@retval EFI_UNSUPPORTED Switching the BSP or a processor to be hot-removed is not supported.
@retval EFI_NOT_FOUND The processor with the handle specified by ProcessorNumber does not exist.
@retval EFI_INVALID_PARAMETER ProcessorNumber is invalid.
**/
EFI_STATUS
EFIAPI
SmmSwitchBsp (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber
)
{
//
// Check parameter
//
if (ProcessorNumber >= mMaxNumberOfCpus) {
return EFI_INVALID_PARAMETER;
}
if (gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID) {
return EFI_NOT_FOUND;
}
if (gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone ||
gSmst->CurrentlyExecutingCpu == ProcessorNumber) {
return EFI_UNSUPPORTED;
}
//
// Setting of the BSP for next SMI is pending until all SMI handlers are finished
//
gSmmCpuPrivate->Operation[ProcessorNumber] = SmmCpuSwitchBsp;
return EFI_SUCCESS;
}
/**
Notify that a processor was hot-added.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[in] ProcessorId Local APIC ID of the hot-added processor.
@param[out] ProcessorNumber The handle number of the hot-added processor.
@retval EFI_SUCCESS The hot-addition of the specified processors was successfully notified.
@retval EFI_UNSUPPORTED Hot addition of processor is not supported.
@retval EFI_NOT_FOUND The processor with the handle specified by ProcessorNumber does not exist.
@retval EFI_INVALID_PARAMETER ProcessorNumber is invalid.
@retval EFI_ALREADY_STARTED The processor is already online in the system.
**/
EFI_STATUS
EFIAPI
SmmAddProcessor (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINT64 ProcessorId,
OUT UINTN *ProcessorNumber
)
{
UINTN Index;
if (!FeaturePcdGet (PcdCpuHotPlugSupport)) {
return EFI_UNSUPPORTED;
}
//
// Check parameter
//
if (ProcessorNumber == NULL || ProcessorId == INVALID_APIC_ID) {
return EFI_INVALID_PARAMETER;
}
//
// Check if the processor already exists
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == ProcessorId) {
return EFI_ALREADY_STARTED;
}
}
//
// Check CPU hot plug data. The CPU RAS handler should have created the mapping
// of the APIC ID to SMBASE.
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (mCpuHotPlugData.ApicId[Index] == ProcessorId &&
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
*ProcessorNumber = Index;
gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
return EFI_SUCCESS;
}
}
return EFI_INVALID_PARAMETER;
}
/**
Notify that a processor was hot-removed.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[in] ProcessorNumber The handle number of the hot-added processor.
@retval EFI_SUCCESS The hot-removal of the specified processors was successfully notified.
@retval EFI_UNSUPPORTED Hot removal of processor is not supported.
@retval EFI_UNSUPPORTED Hot removal of BSP is not supported.
@retval EFI_UNSUPPORTED Hot removal of a processor with pending hot-plug operation is not supported.
@retval EFI_INVALID_PARAMETER ProcessorNumber is invalid.
**/
EFI_STATUS
EFIAPI
SmmRemoveProcessor (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber
)
{
if (!FeaturePcdGet (PcdCpuHotPlugSupport)) {
return EFI_UNSUPPORTED;
}
//
// Check parameter
//
if (ProcessorNumber >= mMaxNumberOfCpus ||
gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID) {
return EFI_INVALID_PARAMETER;
}
//
// Can't remove BSP
//
if (ProcessorNumber == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {
return EFI_UNSUPPORTED;
}
if (gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone) {
return EFI_UNSUPPORTED;
}
gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId = INVALID_APIC_ID;
mCpuHotPlugData.ApicId[ProcessorNumber] = INVALID_APIC_ID;
//
// Removal of the processor from the CPU list is pending until all SMI handlers are finished
//
gSmmCpuPrivate->Operation[ProcessorNumber] = SmmCpuRemove;
return EFI_SUCCESS;
}
/**
This return the handle number for the calling processor.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[out] ProcessorNumber The handle number of currently executing processor.
@retval EFI_SUCCESS The current processor handle number was returned
in ProcessorNumber.
@retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
**/
EFI_STATUS
EFIAPI
SmmWhoAmI (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
OUT UINTN *ProcessorNumber
)
{
UINTN Index;
UINT64 ApicId;
//
// Check parameter
//
if (ProcessorNumber == NULL) {
return EFI_INVALID_PARAMETER;
}
ApicId = GetApicId ();
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == ApicId) {
*ProcessorNumber = Index;
return EFI_SUCCESS;
}
}
//
// This should not happen
//
ASSERT (FALSE);
return EFI_NOT_FOUND;
}
/**
Update the SMM CPU list per the pending operation.
This function is called after return from SMI handlers.
**/
VOID
SmmCpuUpdate (
VOID
)
{
UINTN Index;
//
// Handle pending BSP switch operations
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (gSmmCpuPrivate->Operation[Index] == SmmCpuSwitchBsp) {
gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
mSmmMpSyncData->SwitchBsp = TRUE;
mSmmMpSyncData->CandidateBsp[Index] = TRUE;
}
}
//
// Handle pending hot-add operations
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (gSmmCpuPrivate->Operation[Index] == SmmCpuAdd) {
gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
mNumberOfCpus++;
}
}
//
// Handle pending hot-remove operations
//
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
if (gSmmCpuPrivate->Operation[Index] == SmmCpuRemove) {
gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
mNumberOfCpus--;
}
}
}
/**
Register exception handler.
@param This A pointer to the SMM_CPU_SERVICE_PROTOCOL instance.
@param ExceptionType Defines which interrupt or exception to hook. Type EFI_EXCEPTION_TYPE and
the valid values for this parameter are defined in EFI_DEBUG_SUPPORT_PROTOCOL
of the UEFI 2.0 specification.
@param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER
that is called when a processor interrupt occurs.
If this parameter is NULL, then the handler will be uninstalled.
@retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
@retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
**/
EFI_STATUS
EFIAPI
SmmRegisterExceptionHandler (
IN EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return RegisterCpuInterruptHandler (ExceptionType, InterruptHandler);
}
/**
Initialize SMM CPU Services.
It installs EFI SMM CPU Services Protocol.
@param ImageHandle The firmware allocated handle for the EFI image.
@retval EFI_SUCCESS EFI SMM CPU Services Protocol was installed successfully.
**/
EFI_STATUS
InitializeSmmCpuServices (
IN EFI_HANDLE Handle
)
{
EFI_STATUS Status;
Status = gSmst->SmmInstallProtocolInterface (
&Handle,
&gEfiSmmCpuServiceProtocolGuid,
EFI_NATIVE_INTERFACE,
&mSmmCpuService
);
ASSERT_EFI_ERROR (Status);
return Status;
}

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/** @file
Include file for SMM CPU Services protocol implementation.
Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _CPU_SERVICE_H_
#define _CPU_SERVICE_H_
typedef enum {
SmmCpuNone,
SmmCpuAdd,
SmmCpuRemove,
SmmCpuSwitchBsp
} SMM_CPU_OPERATION;
//
// SMM CPU Service Protocol function prototypes.
//
/**
Gets processor information on the requested processor at the instant this call is made.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[in] ProcessorNumber The handle number of processor.
@param[out] ProcessorInfoBuffer A pointer to the buffer where information for
the requested processor is deposited.
@retval EFI_SUCCESS Processor information was returned.
@retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL.
@retval EFI_INVALID_PARAMETER ProcessorNumber is invalid.
@retval EFI_NOT_FOUND The processor with the handle specified by
ProcessorNumber does not exist in the platform.
**/
EFI_STATUS
EFIAPI
SmmGetProcessorInfo (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber,
OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer
);
/**
This service switches the requested AP to be the BSP since the next SMI.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[in] ProcessorNumber The handle number of AP that is to become the new BSP.
@retval EFI_SUCCESS BSP will be switched in next SMI.
@retval EFI_UNSUPPORTED Switching the BSP or a processor to be hot-removed is not supported.
@retval EFI_NOT_FOUND The processor with the handle specified by ProcessorNumber does not exist.
@retval EFI_INVALID_PARAMETER ProcessorNumber is invalid.
**/
EFI_STATUS
EFIAPI
SmmSwitchBsp (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber
);
/**
Notify that a processor was hot-added.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[in] ProcessorId Local APIC ID of the hot-added processor.
@param[out] ProcessorNumber The handle number of the hot-added processor.
@retval EFI_SUCCESS The hot-addition of the specified processors was successfully notified.
@retval EFI_UNSUPPORTED Hot addition of processor is not supported.
@retval EFI_NOT_FOUND The processor with the handle specified by ProcessorNumber does not exist.
@retval EFI_INVALID_PARAMETER ProcessorNumber is invalid.
@retval EFI_ALREADY_STARTED The processor is already online in the system.
**/
EFI_STATUS
EFIAPI
SmmAddProcessor (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINT64 ProcessorId,
OUT UINTN *ProcessorNumber
);
/**
Notify that a processor was hot-removed.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[in] ProcessorNumber The handle number of the hot-added processor.
@retval EFI_SUCCESS The hot-removal of the specified processors was successfully notified.
@retval EFI_UNSUPPORTED Hot removal of processor is not supported.
@retval EFI_UNSUPPORTED Hot removal of BSP is not supported.
@retval EFI_UNSUPPORTED Hot removal of a processor with pending hot-plug operation is not supported.
@retval EFI_INVALID_PARAMETER ProcessorNumber is invalid.
**/
EFI_STATUS
EFIAPI
SmmRemoveProcessor (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN UINTN ProcessorNumber
);
/**
This return the handle number for the calling processor.
@param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@param[out] ProcessorNumber The handle number of currently executing processor.
@retval EFI_SUCCESS The current processor handle number was returned
in ProcessorNumber.
@retval EFI_INVALID_PARAMETER ProcessorNumber is NULL.
**/
EFI_STATUS
EFIAPI
SmmWhoAmI (
IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,
OUT UINTN *ProcessorNumber
);
/**
Register exception handler.
@param This A pointer to the SMM_CPU_SERVICE_PROTOCOL instance.
@param ExceptionType Defines which interrupt or exception to hook. Type EFI_EXCEPTION_TYPE and
the valid values for this parameter are defined in EFI_DEBUG_SUPPORT_PROTOCOL
of the UEFI 2.0 specification.
@param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER
that is called when a processor interrupt occurs.
If this parameter is NULL, then the handler will be uninstalled.
@retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
@retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.
**/
EFI_STATUS
EFIAPI
SmmRegisterExceptionHandler (
IN EFI_SMM_CPU_SERVICE_PROTOCOL *This,
IN EFI_EXCEPTION_TYPE ExceptionType,
IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
//
// Internal function prototypes
//
/**
Update the SMM CPU list per the pending operation.
This function is called after return from SMI handlers.
**/
VOID
SmmCpuUpdate (
VOID
);
/**
Initialize SMM CPU Services.
It installs EFI SMM CPU Services Protocol.
@param ImageHandle The firmware allocated handle for the EFI image.
@retval EFI_SUCCESS EFI SMM CPU Services Protocol was installed successfully.
**/
EFI_STATUS
InitializeSmmCpuServices (
IN EFI_HANDLE Handle
);
#endif

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/** @file
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _CPU_PISMMCPUDXESMM_H_
#define _CPU_PISMMCPUDXESMM_H_
#include <PiSmm.h>
#include <Protocol/MpService.h>
#include <Protocol/SmmConfiguration.h>
#include <Protocol/SmmCpu.h>
#include <Protocol/SmmAccess2.h>
#include <Protocol/SmmCpuSaveState.h>
#include <Protocol/SmmReadyToLock.h>
#include <Protocol/SmmCpuService.h>
#include <Guid/AcpiS3Context.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/TimerLib.h>
#include <Library/SmmLib.h>
#include <Library/SynchronizationLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PcdLib.h>
#include <Library/CacheMaintenanceLib.h>
#include <Library/MtrrLib.h>
#include <Library/SmmCpuPlatformHookLib.h>
#include <Library/SmmServicesTableLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugAgentLib.h>
#include <Library/HobLib.h>
#include <Library/LocalApicLib.h>
#include <Library/UefiCpuLib.h>
#include <Library/CpuExceptionHandlerLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/SmmCpuFeaturesLib.h>
#include <Library/PeCoffGetEntryPointLib.h>
#include <AcpiCpuData.h>
#include <CpuHotPlugData.h>
#include <Register/Cpuid.h>
#include "CpuService.h"
#include "SmmProfile.h"
//
// MSRs required for configuration of SMM Code Access Check
//
#define EFI_MSR_SMM_MCA_CAP 0x17D
#define SMM_CODE_ACCESS_CHK_BIT BIT58
#define SMM_FEATURE_CONTROL_LOCK_BIT BIT0
#define SMM_CODE_CHK_EN_BIT BIT2
///
/// Page Table Entry
///
#define IA32_PG_P BIT0
#define IA32_PG_RW BIT1
#define IA32_PG_WT BIT3
#define IA32_PG_CD BIT4
#define IA32_PG_A BIT5
#define IA32_PG_PS BIT7
#define IA32_PG_PAT_2M BIT12
#define IA32_PG_PAT_4K IA32_PG_PS
#define IA32_PG_PMNT BIT62
#define IA32_PG_NX BIT63
//
// Size of Task-State Segment defined in IA32 Manual
//
#define TSS_SIZE 104
#define TSS_X64_IST1_OFFSET 36
#define TSS_IA32_CR3_OFFSET 28
#define TSS_IA32_ESP_OFFSET 56
//
// Code select value
//
#define PROTECT_MODE_CODE_SEGMENT 0x08
#define LONG_MODE_CODE_SEGMENT 0x38
//
// The size 0x20 must be bigger than
// the size of template code of SmmInit. Currently,
// the size of SmmInit requires the 0x16 Bytes buffer
// at least.
//
#define BACK_BUF_SIZE 0x20
#define EXCEPTION_VECTOR_NUMBER 0x20
#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL
typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;
#define ARRIVAL_EXCEPTION_BLOCKED 0x1
#define ARRIVAL_EXCEPTION_DELAYED 0x2
#define ARRIVAL_EXCEPTION_SMI_DISABLED 0x4
//
// Private structure for the SMM CPU module that is stored in DXE Runtime memory
// Contains the SMM Configuration Protocols that is produced.
// Contains a mix of DXE and SMM contents. All the fields must be used properly.
//
#define SMM_CPU_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('s', 'c', 'p', 'u')
typedef struct {
UINTN Signature;
EFI_HANDLE SmmCpuHandle;
EFI_PROCESSOR_INFORMATION *ProcessorInfo;
SMM_CPU_OPERATION *Operation;
UINTN *CpuSaveStateSize;
VOID **CpuSaveState;
EFI_SMM_RESERVED_SMRAM_REGION SmmReservedSmramRegion[1];
EFI_SMM_ENTRY_CONTEXT SmmCoreEntryContext;
EFI_SMM_ENTRY_POINT SmmCoreEntry;
EFI_SMM_CONFIGURATION_PROTOCOL SmmConfiguration;
} SMM_CPU_PRIVATE_DATA;
extern SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate;
extern CPU_HOT_PLUG_DATA mCpuHotPlugData;
extern UINTN mMaxNumberOfCpus;
extern UINTN mNumberOfCpus;
extern BOOLEAN mRestoreSmmConfigurationInS3;
extern EFI_SMM_CPU_PROTOCOL mSmmCpu;
///
/// The mode of the CPU at the time an SMI occurs
///
extern UINT8 mSmmSaveStateRegisterLma;
//
// SMM CPU Protocol function prototypes.
//
/**
Read information from the CPU save state.
@param This EFI_SMM_CPU_PROTOCOL instance
@param Width The number of bytes to read from the CPU save state.
@param Register Specifies the CPU register to read form the save state.
@param CpuIndex Specifies the zero-based index of the CPU save state
@param Buffer Upon return, this holds the CPU register value read from the save state.
@retval EFI_SUCCESS The register was read from Save State
@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
@retval EFI_INVALID_PARAMTER This or Buffer is NULL.
**/
EFI_STATUS
EFIAPI
SmmReadSaveState (
IN CONST EFI_SMM_CPU_PROTOCOL *This,
IN UINTN Width,
IN EFI_SMM_SAVE_STATE_REGISTER Register,
IN UINTN CpuIndex,
OUT VOID *Buffer
);
/**
Write data to the CPU save state.
@param This EFI_SMM_CPU_PROTOCOL instance
@param Width The number of bytes to read from the CPU save state.
@param Register Specifies the CPU register to write to the save state.
@param CpuIndex Specifies the zero-based index of the CPU save state
@param Buffer Upon entry, this holds the new CPU register value.
@retval EFI_SUCCESS The register was written from Save State
@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
@retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
**/
EFI_STATUS
EFIAPI
SmmWriteSaveState (
IN CONST EFI_SMM_CPU_PROTOCOL *This,
IN UINTN Width,
IN EFI_SMM_SAVE_STATE_REGISTER Register,
IN UINTN CpuIndex,
IN CONST VOID *Buffer
);
/**
Read a CPU Save State register on the target processor.
This function abstracts the differences that whether the CPU Save State register is in the
IA32 CPU Save State Map or X64 CPU Save State Map.
This function supports reading a CPU Save State register in SMBase relocation handler.
@param[in] CpuIndex Specifies the zero-based index of the CPU save state.
@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
@param[in] Width The number of bytes to read from the CPU save state.
@param[out] Buffer Upon return, this holds the CPU register value read from the save state.
@retval EFI_SUCCESS The register was read from Save State.
@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
@retval EFI_INVALID_PARAMTER This or Buffer is NULL.
**/
EFI_STATUS
EFIAPI
ReadSaveStateRegister (
IN UINTN CpuIndex,
IN EFI_SMM_SAVE_STATE_REGISTER Register,
IN UINTN Width,
OUT VOID *Buffer
);
/**
Write value to a CPU Save State register on the target processor.
This function abstracts the differences that whether the CPU Save State register is in the
IA32 CPU Save State Map or X64 CPU Save State Map.
This function supports writing a CPU Save State register in SMBase relocation handler.
@param[in] CpuIndex Specifies the zero-based index of the CPU save state.
@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
@param[in] Width The number of bytes to read from the CPU save state.
@param[in] Buffer Upon entry, this holds the new CPU register value.
@retval EFI_SUCCESS The register was written to Save State.
@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
@retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.
**/
EFI_STATUS
EFIAPI
WriteSaveStateRegister (
IN UINTN CpuIndex,
IN EFI_SMM_SAVE_STATE_REGISTER Register,
IN UINTN Width,
IN CONST VOID *Buffer
);
//
//
//
typedef struct {
UINT32 Offset;
UINT16 Segment;
UINT16 Reserved;
} IA32_FAR_ADDRESS;
extern IA32_FAR_ADDRESS gSmmJmpAddr;
extern CONST UINT8 gcSmmInitTemplate[];
extern CONST UINT16 gcSmmInitSize;
extern UINT32 gSmmCr0;
extern UINT32 gSmmCr3;
extern UINT32 gSmmCr4;
extern UINTN gSmmInitStack;
/**
Semaphore operation for all processor relocate SMMBase.
**/
VOID
EFIAPI
SmmRelocationSemaphoreComplete (
VOID
);
///
/// The type of SMM CPU Information
///
typedef struct {
SPIN_LOCK Busy;
volatile EFI_AP_PROCEDURE Procedure;
volatile VOID *Parameter;
volatile UINT32 Run;
volatile BOOLEAN Present;
} SMM_CPU_DATA_BLOCK;
typedef enum {
SmmCpuSyncModeTradition,
SmmCpuSyncModeRelaxedAp,
SmmCpuSyncModeMax
} SMM_CPU_SYNC_MODE;
typedef struct {
//
// Pointer to an array. The array should be located immediately after this structure
// so that UC cache-ability can be set together.
//
SMM_CPU_DATA_BLOCK *CpuData;
volatile UINT32 Counter;
volatile UINT32 BspIndex;
volatile BOOLEAN InsideSmm;
volatile BOOLEAN AllCpusInSync;
volatile SMM_CPU_SYNC_MODE EffectiveSyncMode;
volatile BOOLEAN SwitchBsp;
volatile BOOLEAN *CandidateBsp;
} SMM_DISPATCHER_MP_SYNC_DATA;
typedef struct {
SPIN_LOCK SpinLock;
UINT32 MsrIndex;
} MP_MSR_LOCK;
#define SMM_PSD_OFFSET 0xfb00
typedef struct {
UINT64 Signature; // Offset 0x00
UINT16 Reserved1; // Offset 0x08
UINT16 Reserved2; // Offset 0x0A
UINT16 Reserved3; // Offset 0x0C
UINT16 SmmCs; // Offset 0x0E
UINT16 SmmDs; // Offset 0x10
UINT16 SmmSs; // Offset 0x12
UINT16 SmmOtherSegment; // Offset 0x14
UINT16 Reserved4; // Offset 0x16
UINT64 Reserved5; // Offset 0x18
UINT64 Reserved6; // Offset 0x20
UINT64 Reserved7; // Offset 0x28
UINT64 SmmGdtPtr; // Offset 0x30
UINT32 SmmGdtSize; // Offset 0x38
UINT32 Reserved8; // Offset 0x3C
UINT64 Reserved9; // Offset 0x40
UINT64 Reserved10; // Offset 0x48
UINT16 Reserved11; // Offset 0x50
UINT16 Reserved12; // Offset 0x52
UINT32 Reserved13; // Offset 0x54
UINT64 MtrrBaseMaskPtr; // Offset 0x58
} PROCESSOR_SMM_DESCRIPTOR;
extern IA32_DESCRIPTOR gcSmiGdtr;
extern IA32_DESCRIPTOR gcSmiIdtr;
extern VOID *gcSmiIdtrPtr;
extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd;
extern UINT64 gPhyMask;
extern ACPI_CPU_DATA mAcpiCpuData;
extern SMM_DISPATCHER_MP_SYNC_DATA *mSmmMpSyncData;
extern VOID *mGdtForAp;
extern VOID *mIdtForAp;
extern VOID *mMachineCheckHandlerForAp;
extern UINTN mSmmStackArrayBase;
extern UINTN mSmmStackArrayEnd;
extern UINTN mSmmStackSize;
extern EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService;
extern IA32_DESCRIPTOR gcSmiInitGdtr;
/**
Create 4G PageTable in SMRAM.
@param ExtraPages Additional page numbers besides for 4G memory
@return PageTable Address
**/
UINT32
Gen4GPageTable (
IN UINTN ExtraPages
);
/**
Initialize global data for MP synchronization.
@param Stacks Base address of SMI stack buffer for all processors.
@param StackSize Stack size for each processor in SMM.
**/
UINT32
InitializeMpServiceData (
IN VOID *Stacks,
IN UINTN StackSize
);
/**
Initialize Timer for SMM AP Sync.
**/
VOID
InitializeSmmTimer (
VOID
);
/**
Start Timer for SMM AP Sync.
**/
UINT64
EFIAPI
StartSyncTimer (
VOID
);
/**
Check if the SMM AP Sync timer is timeout.
@param Timer The start timer from the begin.
**/
BOOLEAN
EFIAPI
IsSyncTimerTimeout (
IN UINT64 Timer
);
/**
Initialize IDT for SMM Stack Guard.
**/
VOID
EFIAPI
InitializeIDTSmmStackGuard (
VOID
);
/**
Register the SMM Foundation entry point.
@param This Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
@param SmmEntryPoint SMM Foundation EntryPoint
@retval EFI_SUCCESS Successfully to register SMM foundation entry point
**/
EFI_STATUS
EFIAPI
RegisterSmmEntry (
IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This,
IN EFI_SMM_ENTRY_POINT SmmEntryPoint
);
/**
Create PageTable for SMM use.
@return PageTable Address
**/
UINT32
SmmInitPageTable (
VOID
);
/**
Schedule a procedure to run on the specified CPU.
@param Procedure The address of the procedure to run
@param CpuIndex Target CPU number
@param ProcArguments The parameter to pass to the procedure
@retval EFI_INVALID_PARAMETER CpuNumber not valid
@retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
@retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
@retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
@retval EFI_SUCCESS - The procedure has been successfully scheduled
**/
EFI_STATUS
EFIAPI
SmmStartupThisAp (
IN EFI_AP_PROCEDURE Procedure,
IN UINTN CpuIndex,
IN OUT VOID *ProcArguments OPTIONAL
);
/**
Schedule a procedure to run on the specified CPU in a blocking fashion.
@param Procedure The address of the procedure to run
@param CpuIndex Target CPU Index
@param ProcArguments The parameter to pass to the procedure
@retval EFI_INVALID_PARAMETER CpuNumber not valid
@retval EFI_INVALID_PARAMETER CpuNumber specifying BSP
@retval EFI_INVALID_PARAMETER The AP specified by CpuNumber did not enter SMM
@retval EFI_INVALID_PARAMETER The AP specified by CpuNumber is busy
@retval EFI_SUCCESS The procedure has been successfully scheduled
**/
EFI_STATUS
EFIAPI
SmmBlockingStartupThisAp (
IN EFI_AP_PROCEDURE Procedure,
IN UINTN CpuIndex,
IN OUT VOID *ProcArguments OPTIONAL
);
/**
Initialize MP synchronization data.
**/
VOID
EFIAPI
InitializeMpSyncData (
VOID
);
/**
Find out SMRAM information including SMRR base and SMRR size.
@param SmrrBase SMRR base
@param SmrrSize SMRR size
**/
VOID
FindSmramInfo (
OUT UINT32 *SmrrBase,
OUT UINT32 *SmrrSize
);
/**
The function is invoked before SMBASE relocation in S3 path to restores CPU status.
The function is invoked before SMBASE relocation in S3 path. It does first time microcode load
and restores MTRRs for both BSP and APs.
**/
VOID
EarlyInitializeCpu (
VOID
);
/**
The function is invoked after SMBASE relocation in S3 path to restores CPU status.
The function is invoked after SMBASE relocation in S3 path. It restores configuration according to
data saved by normal boot path for both BSP and APs.
**/
VOID
InitializeCpu (
VOID
);
/**
Page Fault handler for SMM use.
@param InterruptType Defines the type of interrupt or exception that
occurred on the processor.This parameter is processor architecture specific.
@param SystemContext A pointer to the processor context when
the interrupt occurred on the processor.
**/
VOID
EFIAPI
SmiPFHandler (
IN EFI_EXCEPTION_TYPE InterruptType,
IN EFI_SYSTEM_CONTEXT SystemContext
);
/**
Perform the remaining tasks.
**/
VOID
PerformRemainingTasks (
VOID
);
/**
Initialize MSR spin lock by MSR index.
@param MsrIndex MSR index value.
**/
VOID
InitMsrSpinLockByIndex (
IN UINT32 MsrIndex
);
/**
Hook return address of SMM Save State so that semaphore code
can be executed immediately after AP exits SMM to indicate to
the BSP that an AP has exited SMM after SMBASE relocation.
@param[in] CpuIndex The processor index.
@param[in] RebasedFlag A pointer to a flag that is set to TRUE
immediately after AP exits SMM.
**/
VOID
SemaphoreHook (
IN UINTN CpuIndex,
IN volatile BOOLEAN *RebasedFlag
);
/**
Configure SMM Code Access Check feature for all processors.
SMM Feature Control MSR will be locked after configuration.
**/
VOID
ConfigSmmCodeAccessCheck (
VOID
);
/**
Hook the code executed immediately after an RSM instruction on the currently
executing CPU. The mode of code executed immediately after RSM must be
detected, and the appropriate hook must be selected. Always clear the auto
HALT restart flag if it is set.
@param[in] CpuIndex The processor index for the currently
executing CPU.
@param[in] CpuState Pointer to SMRAM Save State Map for the
currently executing CPU.
@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
32-bit mode from 64-bit SMM.
@param[in] NewInstructionPointer Instruction pointer to use if resuming to
same mode as SMM.
@retval The value of the original instruction pointer before it was hooked.
**/
UINT64
EFIAPI
HookReturnFromSmm (
IN UINTN CpuIndex,
SMRAM_SAVE_STATE_MAP *CpuState,
UINT64 NewInstructionPointer32,
UINT64 NewInstructionPointer
);
/**
Get the size of the SMI Handler in bytes.
@retval The size, in bytes, of the SMI Handler.
**/
UINTN
EFIAPI
GetSmiHandlerSize (
VOID
);
/**
Install the SMI handler for the CPU specified by CpuIndex. This function
is called by the CPU that was elected as monarch during System Management
Mode initialization.
@param[in] CpuIndex The index of the CPU to install the custom SMI handler.
The value must be between 0 and the NumberOfCpus field
in the System Management System Table (SMST).
@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
@param[in] SmiStack The stack to use when an SMI is processed by the
the CPU specified by CpuIndex.
@param[in] StackSize The size, in bytes, if the stack used when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] GdtBase The base address of the GDT to use when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] IdtBase The base address of the IDT to use when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] Cr3 The base address of the page tables to use when an SMI
is processed by the CPU specified by CpuIndex.
**/
VOID
EFIAPI
InstallSmiHandler (
IN UINTN CpuIndex,
IN UINT32 SmBase,
IN VOID *SmiStack,
IN UINTN StackSize,
IN UINTN GdtBase,
IN UINTN GdtSize,
IN UINTN IdtBase,
IN UINTN IdtSize,
IN UINT32 Cr3
);
/**
Search module name by input IP address and output it.
@param CallerIpAddress Caller instruction pointer.
**/
VOID
DumpModuleInfoByIp (
IN UINTN CallerIpAddress
);
#endif

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## @file
# CPU SMM driver.
#
# This SMM driver performs SMM initialization, deploy SMM Entry Vector,
# provides CPU specific services in SMM.
#
# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PiSmmCpuDxeSmm
MODULE_UNI_FILE = PiSmmCpuDxeSmm.uni
FILE_GUID = A3FF0EF5-0C28-42f5-B544-8C7DE1E80014
MODULE_TYPE = DXE_SMM_DRIVER
VERSION_STRING = 1.0
PI_SPECIFICATION_VERSION = 0x0001000A
ENTRY_POINT = PiCpuSmmEntry
#
# The following information is for reference only and not required by the build tools.
#
# VALID_ARCHITECTURES = IA32 X64
#
[Sources]
PiSmmCpuDxeSmm.c
PiSmmCpuDxeSmm.h
MpService.c
SyncTimer.c
CpuS3.c
CpuService.c
CpuService.h
SmmProfile.c
SmmProfile.h
SmmProfileInternal.h
SmramSaveState.c
[Sources.Ia32]
Ia32/Semaphore.c
Ia32/PageTbl.c
Ia32/SmmProfileArch.c
Ia32/SmmProfileArch.h
Ia32/SmmInit.asm | MSFT
Ia32/SmiEntry.asm | MSFT
Ia32/SmiException.asm | MSFT
Ia32/MpFuncs.asm | MSFT
Ia32/SmmInit.asm | INTEL
Ia32/SmiEntry.asm | INTEL
Ia32/SmiException.asm | INTEL
Ia32/MpFuncs.asm | INTEL
Ia32/SmmInit.S | GCC
Ia32/SmiEntry.S | GCC
Ia32/SmiException.S | GCC
Ia32/MpFuncs.S | GCC
[Sources.X64]
X64/Semaphore.c
X64/PageTbl.c
X64/SmmProfileArch.c
X64/SmmProfileArch.h
X64/SmmInit.asm | MSFT
X64/SmiEntry.asm | MSFT
X64/SmiException.asm | MSFT
X64/MpFuncs.asm | MSFT
X64/SmmInit.asm | INTEL
X64/SmiEntry.asm | INTEL
X64/SmiException.asm | INTEL
X64/MpFuncs.asm | INTEL
X64/SmmInit.S | GCC
X64/SmiEntry.S | GCC
X64/SmiException.S | GCC
X64/MpFuncs.S | GCC
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
IntelFrameworkPkg/IntelFrameworkPkg.dec
[LibraryClasses]
UefiDriverEntryPoint
UefiRuntimeServicesTableLib
CacheMaintenanceLib
PcdLib
DebugLib
BaseLib
SynchronizationLib
BaseMemoryLib
MtrrLib
SmmLib
IoLib
TimerLib
SmmServicesTableLib
MemoryAllocationLib
DebugAgentLib
HobLib
PciLib
LocalApicLib
UefiCpuLib
SmmCpuPlatformHookLib
CpuExceptionHandlerLib
UefiLib
DxeServicesTableLib
CpuLib
ReportStatusCodeLib
SmmCpuFeaturesLib
PeCoffGetEntryPointLib
[Protocols]
gEfiSmmAccess2ProtocolGuid ## CONSUMES
gEfiMpServiceProtocolGuid ## CONSUMES
gEfiSmmConfigurationProtocolGuid ## PRODUCES
gEfiSmmCpuProtocolGuid ## PRODUCES
gEfiSmmReadyToLockProtocolGuid ## NOTIFY
gEfiSmmCpuServiceProtocolGuid ## PRODUCES
gEfiSmmCpuSaveStateProtocolGuid ## SOMETIMES_PRODUCES
[Guids]
gEfiAcpiVariableGuid ## SOMETIMES_CONSUMES ## HOB # it is used for S3 boot.
gEfiGlobalVariableGuid ## SOMETIMES_PRODUCES ## Variable:L"SmmProfileData"
gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## SystemTable
gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## SystemTable
[FeaturePcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock ## CONSUMES
[Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress ## SOMETIMES_CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress ## SOMETIMES_PRODUCES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable ## CONSUMES
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode ## CONSUMES
[Depex]
gEfiMpServiceProtocolGuid
[UserExtensions.TianoCore."ExtraFiles"]
PiSmmCpuDxeSmmExtra.uni

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/** @file
SMM profile header file.
Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SMM_PROFILE_H_
#define _SMM_PROFILE_H_
#include "SmmProfileInternal.h"
///
/// MSR Register Index
///
#define MSR_IA32_MISC_ENABLE 0x1A0
//
// External functions
//
/**
Initialize processor environment for SMM profile.
@param CpuIndex The index of the processor.
**/
VOID
ActivateSmmProfile (
IN UINTN CpuIndex
);
/**
Initialize SMM profile in SMM CPU entry point.
@param[in] Cr3 The base address of the page tables to use in SMM.
**/
VOID
InitSmmProfile (
UINT32 Cr3
);
/**
Increase SMI number in each SMI entry.
**/
VOID
SmmProfileRecordSmiNum (
VOID
);
/**
The Page fault handler to save SMM profile data.
@param Rip The RIP when exception happens.
@param ErrorCode The Error code of exception.
**/
VOID
SmmProfilePFHandler (
UINTN Rip,
UINTN ErrorCode
);
/**
Updates page table to make some memory ranges (like system memory) absent
and make some memory ranges (like MMIO) present and execute disable. It also
update 2MB-page to 4KB-page for some memory ranges.
**/
VOID
SmmProfileStart (
VOID
);
/**
Page fault IDT handler for SMM Profile.
**/
VOID
EFIAPI
PageFaultIdtHandlerSmmProfile (
VOID
);
/**
Check if XD feature is supported by a processor.
**/
VOID
CheckFeatureSupported (
VOID
);
/**
Enable XD feature.
**/
VOID
ActivateXd (
VOID
);
/**
Update page table according to protected memory ranges and the 4KB-page mapped memory ranges.
**/
VOID
InitPaging (
VOID
);
/**
Check if XD and BTS features are supported by all processors.
**/
VOID
CheckProcessorFeature (
VOID
);
extern BOOLEAN mXdSupported;
extern BOOLEAN mXdEnabled;
#endif // _SMM_PROFILE_H_

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/** @file
SMM profile internal header file.
Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef _SMM_PROFILE_INTERNAL_H_
#define _SMM_PROFILE_INTERNAL_H_
#include <Guid/GlobalVariable.h>
#include <Guid/Acpi.h>
#include <Protocol/SmmReadyToLock.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/CpuLib.h>
#include <IndustryStandard/Acpi.h>
#include "SmmProfileArch.h"
//
// Configure the SMM_PROFILE DTS region size
//
#define SMM_PROFILE_DTS_SIZE (4 * 1024 * 1024) // 4M
#define MAX_PF_PAGE_COUNT 0x2
#define PEBS_RECORD_NUMBER 0x2
#define MAX_PF_ENTRY_COUNT 10
//
// This MACRO just enable unit test for the profile
// Please disable it.
//
#define IA32_PF_EC_P (1u << 0)
#define IA32_PF_EC_WR (1u << 1)
#define IA32_PF_EC_US (1u << 2)
#define IA32_PF_EC_RSVD (1u << 3)
#define IA32_PF_EC_ID (1u << 4)
#define SMM_PROFILE_NAME L"SmmProfileData"
//
// CPU generic definition
//
#define CPUID1_EDX_XD_SUPPORT 0x100000
#define MSR_EFER 0xc0000080
#define MSR_EFER_XD 0x800
#define CPUID1_EDX_BTS_AVAILABLE 0x200000
#define DR6_SINGLE_STEP 0x4000
#define RFLAG_TF 0x100
#define MSR_DEBUG_CTL 0x1D9
#define MSR_DEBUG_CTL_LBR 0x1
#define MSR_DEBUG_CTL_TR 0x40
#define MSR_DEBUG_CTL_BTS 0x80
#define MSR_DEBUG_CTL_BTINT 0x100
#define MSR_LASTBRANCH_TOS 0x1C9
#define MSR_LER_FROM_LIP 0x1DD
#define MSR_LER_TO_LIP 0x1DE
#define MSR_DS_AREA 0x600
typedef struct {
EFI_PHYSICAL_ADDRESS Base;
EFI_PHYSICAL_ADDRESS Top;
} MEMORY_RANGE;
typedef struct {
MEMORY_RANGE Range;
BOOLEAN Present;
BOOLEAN Nx;
} MEMORY_PROTECTION_RANGE;
typedef struct {
UINT64 HeaderSize;
UINT64 MaxDataEntries;
UINT64 MaxDataSize;
UINT64 CurDataEntries;
UINT64 CurDataSize;
UINT64 TsegStart;
UINT64 TsegSize;
UINT64 NumSmis;
UINT64 NumCpus;
} SMM_PROFILE_HEADER;
typedef struct {
UINT64 SmiNum;
UINT64 CpuNum;
UINT64 ApicId;
UINT64 ErrorCode;
UINT64 Instruction;
UINT64 Address;
UINT64 SmiCmd;
} SMM_PROFILE_ENTRY;
extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;
extern UINTN gSmiExceptionHandlers[];
extern BOOLEAN mXdSupported;
extern UINTN *mPFEntryCount;
extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];
extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];
//
// Internal functions
//
/**
Update IDT table to replace page fault handler and INT 1 handler.
**/
VOID
InitIdtr (
VOID
);
/**
Check if the memory address will be mapped by 4KB-page.
@param Address The address of Memory.
**/
BOOLEAN
IsAddressSplit (
IN EFI_PHYSICAL_ADDRESS Address
);
/**
Check if the memory address will be mapped by 4KB-page.
@param Address The address of Memory.
@param Nx The flag indicates if the memory is execute-disable.
**/
BOOLEAN
IsAddressValid (
IN EFI_PHYSICAL_ADDRESS Address,
IN BOOLEAN *Nx
);
/**
Page Fault handler for SMM use.
**/
VOID
SmiDefaultPFHandler (
VOID
);
/**
Clear TF in FLAGS.
@param SystemContext A pointer to the processor context when
the interrupt occurred on the processor.
**/
VOID
ClearTrapFlag (
IN OUT EFI_SYSTEM_CONTEXT SystemContext
);
#endif // _SMM_PROFILE_H_

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/** @file
Provides services to access SMRAM Save State Map
Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <PiSmm.h>
#include <Library/SmmCpuFeaturesLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/SmmServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Register/Cpuid.h>
#include <Register/SmramSaveStateMap.h>
//
// EFER register LMA bit
//
#define LMA BIT10
///
/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
///
#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)
///
/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE
///
#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }
///
/// Structure used to describe a range of registers
///
typedef struct {
EFI_SMM_SAVE_STATE_REGISTER Start;
EFI_SMM_SAVE_STATE_REGISTER End;
UINTN Length;
} CPU_SMM_SAVE_STATE_REGISTER_RANGE;
///
/// Structure used to build a lookup table to retrieve the widths and offsets
/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value
///
#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1
#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2
#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3
#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4
typedef struct {
UINT8 Width32;
UINT8 Width64;
UINT16 Offset32;
UINT16 Offset64Lo;
UINT16 Offset64Hi;
BOOLEAN Writeable;
} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;
///
/// Structure used to build a lookup table for the IOMisc width information
///
typedef struct {
UINT8 Width;
EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth;
} CPU_SMM_SAVE_STATE_IO_WIDTH;
///
/// Variables from SMI Handler
///
extern UINT32 gSmbase;
extern volatile UINT32 gSmiStack;
extern UINT32 gSmiCr3;
extern volatile UINT8 gcSmiHandlerTemplate[];
extern CONST UINT16 gcSmiHandlerSize;
//
// Variables used by SMI Handler
//
IA32_DESCRIPTOR gSmiHandlerIdtr;
///
/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER
/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
///
CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),
{ (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
};
///
/// Lookup table used to retrieve the widths and offsets associated with each
/// supported EFI_SMM_SAVE_STATE_REGISTER value
///
CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {
{0, 0, 0, 0, 0, FALSE}, // Reserved
//
// Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.
//
{4, 4, SMM_CPU_OFFSET (x86.SMMRevId) , SMM_CPU_OFFSET (x64.SMMRevId) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX = 1
{4, 4, SMM_CPU_OFFSET (x86.IOMisc) , SMM_CPU_OFFSET (x64.IOMisc) , 0 , FALSE}, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX = 2
{4, 8, SMM_CPU_OFFSET (x86.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE}, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3
//
// CPU Save State registers defined in PI SMM CPU Protocol.
//
{0, 8, 0 , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTBASE = 4
{0, 8, 0 , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTBASE = 5
{0, 8, 0 , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTBASE = 6
{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7
{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8
{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9
{0, 0, 0 , 0 , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTINFO = 10
{4, 4, SMM_CPU_OFFSET (x86._ES) , SMM_CPU_OFFSET (x64._ES) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_ES = 20
{4, 4, SMM_CPU_OFFSET (x86._CS) , SMM_CPU_OFFSET (x64._CS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CS = 21
{4, 4, SMM_CPU_OFFSET (x86._SS) , SMM_CPU_OFFSET (x64._SS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_SS = 22
{4, 4, SMM_CPU_OFFSET (x86._DS) , SMM_CPU_OFFSET (x64._DS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DS = 23
{4, 4, SMM_CPU_OFFSET (x86._FS) , SMM_CPU_OFFSET (x64._FS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_FS = 24
{4, 4, SMM_CPU_OFFSET (x86._GS) , SMM_CPU_OFFSET (x64._GS) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_GS = 25
{0, 4, 0 , SMM_CPU_OFFSET (x64._LDTR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26
{4, 4, SMM_CPU_OFFSET (x86._TR) , SMM_CPU_OFFSET (x64._TR) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_TR_SEL = 27
{4, 8, SMM_CPU_OFFSET (x86._DR7) , SMM_CPU_OFFSET (x64._DR7) , SMM_CPU_OFFSET (x64._DR7) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR7 = 28
{4, 8, SMM_CPU_OFFSET (x86._DR6) , SMM_CPU_OFFSET (x64._DR6) , SMM_CPU_OFFSET (x64._DR6) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_DR6 = 29
{0, 8, 0 , SMM_CPU_OFFSET (x64._R8) , SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R8 = 30
{0, 8, 0 , SMM_CPU_OFFSET (x64._R9) , SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R9 = 31
{0, 8, 0 , SMM_CPU_OFFSET (x64._R10) , SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R10 = 32
{0, 8, 0 , SMM_CPU_OFFSET (x64._R11) , SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R11 = 33
{0, 8, 0 , SMM_CPU_OFFSET (x64._R12) , SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R12 = 34
{0, 8, 0 , SMM_CPU_OFFSET (x64._R13) , SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R13 = 35
{0, 8, 0 , SMM_CPU_OFFSET (x64._R14) , SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R14 = 36
{0, 8, 0 , SMM_CPU_OFFSET (x64._R15) , SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_R15 = 37
{4, 8, SMM_CPU_OFFSET (x86._EAX) , SMM_CPU_OFFSET (x64._RAX) , SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RAX = 38
{4, 8, SMM_CPU_OFFSET (x86._EBX) , SMM_CPU_OFFSET (x64._RBX) , SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBX = 39
{4, 8, SMM_CPU_OFFSET (x86._ECX) , SMM_CPU_OFFSET (x64._RCX) , SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RCX = 40
{4, 8, SMM_CPU_OFFSET (x86._EDX) , SMM_CPU_OFFSET (x64._RDX) , SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDX = 41
{4, 8, SMM_CPU_OFFSET (x86._ESP) , SMM_CPU_OFFSET (x64._RSP) , SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSP = 42
{4, 8, SMM_CPU_OFFSET (x86._EBP) , SMM_CPU_OFFSET (x64._RBP) , SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RBP = 43
{4, 8, SMM_CPU_OFFSET (x86._ESI) , SMM_CPU_OFFSET (x64._RSI) , SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RSI = 44
{4, 8, SMM_CPU_OFFSET (x86._EDI) , SMM_CPU_OFFSET (x64._RDI) , SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RDI = 45
{4, 8, SMM_CPU_OFFSET (x86._EIP) , SMM_CPU_OFFSET (x64._RIP) , SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RIP = 46
{4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_REGISTER_RFLAGS = 51
{4, 8, SMM_CPU_OFFSET (x86._CR0) , SMM_CPU_OFFSET (x64._CR0) , SMM_CPU_OFFSET (x64._CR0) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR0 = 52
{4, 8, SMM_CPU_OFFSET (x86._CR3) , SMM_CPU_OFFSET (x64._CR3) , SMM_CPU_OFFSET (x64._CR3) + 4, FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR3 = 53
{0, 4, 0 , SMM_CPU_OFFSET (x64._CR4) , 0 , FALSE}, // EFI_SMM_SAVE_STATE_REGISTER_CR4 = 54
};
///
/// Lookup table for the IOMisc width information
///
CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = {
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 0
{ 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE = 1
{ 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD = 2
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 3
{ 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 }, // SMM_IO_LENGTH_DWORD = 4
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 5
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined = 6
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined = 7
};
///
/// Lookup table for the IOMisc type information
///
CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = {
EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX = 0
EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX = 1
EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS = 2
EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS = 3
(EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 4
(EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 5
EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS = 6
EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS = 7
EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 8
EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_OUT_IMMEDIATE = 9
(EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 10
(EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 11
(EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 12
(EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 13
(EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined = 14
(EFI_SMM_SAVE_STATE_IO_TYPE)0 // Undefined = 15
};
///
/// The mode of the CPU at the time an SMI occurs
///
UINT8 mSmmSaveStateRegisterLma;
/**
Read information from the CPU save state.
@param Register Specifies the CPU register to read form the save state.
@retval 0 Register is not valid
@retval >0 Index into mSmmCpuWidthOffset[] associated with Register
**/
UINTN
GetRegisterIndex (
IN EFI_SMM_SAVE_STATE_REGISTER Register
)
{
UINTN Index;
UINTN Offset;
for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {
if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {
return Register - mSmmCpuRegisterRanges[Index].Start + Offset;
}
Offset += mSmmCpuRegisterRanges[Index].Length;
}
return 0;
}
/**
Read a CPU Save State register on the target processor.
This function abstracts the differences that whether the CPU Save State register is in the
IA32 CPU Save State Map or X64 CPU Save State Map.
This function supports reading a CPU Save State register in SMBase relocation handler.
@param[in] CpuIndex Specifies the zero-based index of the CPU save state.
@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
@param[in] Width The number of bytes to read from the CPU save state.
@param[out] Buffer Upon return, this holds the CPU register value read from the save state.
@retval EFI_SUCCESS The register was read from Save State.
@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
@retval EFI_INVALID_PARAMTER This or Buffer is NULL.
**/
EFI_STATUS
ReadSaveStateRegisterByIndex (
IN UINTN CpuIndex,
IN UINTN RegisterIndex,
IN UINTN Width,
OUT VOID *Buffer
)
{
SMRAM_SAVE_STATE_MAP *CpuSaveState;
if (RegisterIndex == 0) {
return EFI_NOT_FOUND;
}
CpuSaveState = gSmst->CpuSaveState[CpuIndex];
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
//
// If 32-bit mode width is zero, then the specified register can not be accessed
//
if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
return EFI_NOT_FOUND;
}
//
// If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
//
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
return EFI_INVALID_PARAMETER;
}
//
// Write return buffer
//
ASSERT(CpuSaveState != NULL);
CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);
} else {
//
// If 64-bit mode width is zero, then the specified register can not be accessed
//
if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
return EFI_NOT_FOUND;
}
//
// If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
//
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
return EFI_INVALID_PARAMETER;
}
//
// Write lower 32-bits of return buffer
//
CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));
if (Width >= 4) {
//
// Write upper 32-bits of return buffer
//
CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);
}
}
return EFI_SUCCESS;
}
/**
Read a CPU Save State register on the target processor.
This function abstracts the differences that whether the CPU Save State register is in the
IA32 CPU Save State Map or X64 CPU Save State Map.
This function supports reading a CPU Save State register in SMBase relocation handler.
@param[in] CpuIndex Specifies the zero-based index of the CPU save state.
@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
@param[in] Width The number of bytes to read from the CPU save state.
@param[out] Buffer Upon return, this holds the CPU register value read from the save state.
@retval EFI_SUCCESS The register was read from Save State.
@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
@retval EFI_INVALID_PARAMTER This or Buffer is NULL.
**/
EFI_STATUS
EFIAPI
ReadSaveStateRegister (
IN UINTN CpuIndex,
IN EFI_SMM_SAVE_STATE_REGISTER Register,
IN UINTN Width,
OUT VOID *Buffer
)
{
UINT32 SmmRevId;
SMRAM_SAVE_STATE_IOMISC IoMisc;
EFI_SMM_SAVE_STATE_IO_INFO *IoInfo;
VOID *IoMemAddr;
//
// Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA
//
if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
//
// Only byte access is supported for this register
//
if (Width != 1) {
return EFI_INVALID_PARAMETER;
}
*(UINT8 *)Buffer = mSmmSaveStateRegisterLma;
return EFI_SUCCESS;
}
//
// Check for special EFI_SMM_SAVE_STATE_REGISTER_IO
//
if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
//
// Get SMM Revision ID
//
ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof(SmmRevId), &SmmRevId);
//
// See if the CPU supports the IOMisc register in the save state
//
if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) {
return EFI_NOT_FOUND;
}
//
// Get the IOMisc register value
//
ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof(IoMisc.Uint32), &IoMisc.Uint32);
//
// Check for the SMI_FLAG in IOMisc
//
if (IoMisc.Bits.SmiFlag == 0) {
return EFI_NOT_FOUND;
}
//
// Compute index for the I/O Length and I/O Type lookup tables
//
if (mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0 || mSmmCpuIoType[IoMisc.Bits.Type] == 0) {
return EFI_NOT_FOUND;
}
//
// Zero the IoInfo structure that will be returned in Buffer
//
IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;
ZeroMem (IoInfo, sizeof(EFI_SMM_SAVE_STATE_IO_INFO));
//
// Use lookup tables to help fill in all the fields of the IoInfo structure
//
IoInfo->IoPort = (UINT16)IoMisc.Bits.Port;
IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth;
IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type];
if (IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_INPUT || IoInfo->IoType == EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT) {
ReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData);
}
else {
ReadSaveStateRegisterByIndex(CpuIndex, SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX, sizeof(IoMemAddr), &IoMemAddr);
CopyMem(&IoInfo->IoData, IoMemAddr, mSmmCpuIoWidth[IoMisc.Bits.Length].Width);
}
return EFI_SUCCESS;
}
//
// Convert Register to a register lookup table index
//
return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex (Register), Width, Buffer);
}
/**
Write value to a CPU Save State register on the target processor.
This function abstracts the differences that whether the CPU Save State register is in the
IA32 CPU Save State Map or X64 CPU Save State Map.
This function supports writing a CPU Save State register in SMBase relocation handler.
@param[in] CpuIndex Specifies the zero-based index of the CPU save state.
@param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table.
@param[in] Width The number of bytes to read from the CPU save state.
@param[in] Buffer Upon entry, this holds the new CPU register value.
@retval EFI_SUCCESS The register was written to Save State.
@retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.
@retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct.
**/
EFI_STATUS
EFIAPI
WriteSaveStateRegister (
IN UINTN CpuIndex,
IN EFI_SMM_SAVE_STATE_REGISTER Register,
IN UINTN Width,
IN CONST VOID *Buffer
)
{
UINTN RegisterIndex;
SMRAM_SAVE_STATE_MAP *CpuSaveState;
//
// Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored
//
if (Register == EFI_SMM_SAVE_STATE_REGISTER_LMA) {
return EFI_SUCCESS;
}
//
// Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported
//
if (Register == EFI_SMM_SAVE_STATE_REGISTER_IO) {
return EFI_NOT_FOUND;
}
//
// Convert Register to a register lookup table index
//
RegisterIndex = GetRegisterIndex (Register);
if (RegisterIndex == 0) {
return EFI_NOT_FOUND;
}
CpuSaveState = gSmst->CpuSaveState[CpuIndex];
//
// Do not write non-writable SaveState, because it will cause exception.
//
if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) {
return EFI_UNSUPPORTED;
}
//
// Check CPU mode
//
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
//
// If 32-bit mode width is zero, then the specified register can not be accessed
//
if (mSmmCpuWidthOffset[RegisterIndex].Width32 == 0) {
return EFI_NOT_FOUND;
}
//
// If Width is bigger than the 32-bit mode width, then the specified register can not be accessed
//
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {
return EFI_INVALID_PARAMETER;
}
//
// Write SMM State register
//
ASSERT (CpuSaveState != NULL);
CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);
} else {
//
// If 64-bit mode width is zero, then the specified register can not be accessed
//
if (mSmmCpuWidthOffset[RegisterIndex].Width64 == 0) {
return EFI_NOT_FOUND;
}
//
// If Width is bigger than the 64-bit mode width, then the specified register can not be accessed
//
if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) {
return EFI_INVALID_PARAMETER;
}
//
// Write lower 32-bits of SMM State register
//
CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));
if (Width >= 4) {
//
// Write upper 32-bits of SMM State register
//
CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);
}
}
return EFI_SUCCESS;
}
/**
Hook the code executed immediately after an RSM instruction on the currently
executing CPU. The mode of code executed immediately after RSM must be
detected, and the appropriate hook must be selected. Always clear the auto
HALT restart flag if it is set.
@param[in] CpuIndex The processor index for the currently
executing CPU.
@param[in] CpuState Pointer to SMRAM Save State Map for the
currently executing CPU.
@param[in] NewInstructionPointer32 Instruction pointer to use if resuming to
32-bit mode from 64-bit SMM.
@param[in] NewInstructionPointer Instruction pointer to use if resuming to
same mode as SMM.
@retval The value of the original instruction pointer before it was hooked.
**/
UINT64
EFIAPI
HookReturnFromSmm (
IN UINTN CpuIndex,
SMRAM_SAVE_STATE_MAP *CpuState,
UINT64 NewInstructionPointer32,
UINT64 NewInstructionPointer
)
{
UINT64 OriginalInstructionPointer;
OriginalInstructionPointer = SmmCpuFeaturesHookReturnFromSmm (
CpuIndex,
CpuState,
NewInstructionPointer32,
NewInstructionPointer
);
if (OriginalInstructionPointer != 0) {
return OriginalInstructionPointer;
}
if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {
OriginalInstructionPointer = (UINT64)CpuState->x86._EIP;
CpuState->x86._EIP = (UINT32)NewInstructionPointer;
//
// Clear the auto HALT restart flag so the RSM instruction returns
// program control to the instruction following the HLT instruction.
//
if ((CpuState->x86.AutoHALTRestart & BIT0) != 0) {
CpuState->x86.AutoHALTRestart &= ~BIT0;
}
} else {
OriginalInstructionPointer = CpuState->x64._RIP;
if ((CpuState->x64.IA32_EFER & LMA) == 0) {
CpuState->x64._RIP = (UINT32)NewInstructionPointer32;
} else {
CpuState->x64._RIP = (UINT32)NewInstructionPointer;
}
//
// Clear the auto HALT restart flag so the RSM instruction returns
// program control to the instruction following the HLT instruction.
//
if ((CpuState->x64.AutoHALTRestart & BIT0) != 0) {
CpuState->x64.AutoHALTRestart &= ~BIT0;
}
}
return OriginalInstructionPointer;
}
/**
Get the size of the SMI Handler in bytes.
@retval The size, in bytes, of the SMI Handler.
**/
UINTN
EFIAPI
GetSmiHandlerSize (
VOID
)
{
UINTN Size;
Size = SmmCpuFeaturesGetSmiHandlerSize ();
if (Size != 0) {
return Size;
}
return gcSmiHandlerSize;
}
/**
Install the SMI handler for the CPU specified by CpuIndex. This function
is called by the CPU that was elected as monarch during System Management
Mode initialization.
@param[in] CpuIndex The index of the CPU to install the custom SMI handler.
The value must be between 0 and the NumberOfCpus field
in the System Management System Table (SMST).
@param[in] SmBase The SMBASE address for the CPU specified by CpuIndex.
@param[in] SmiStack The stack to use when an SMI is processed by the
the CPU specified by CpuIndex.
@param[in] StackSize The size, in bytes, if the stack used when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] GdtBase The base address of the GDT to use when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] GdtSize The size, in bytes, of the GDT used when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] IdtBase The base address of the IDT to use when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] IdtSize The size, in bytes, of the IDT used when an SMI is
processed by the CPU specified by CpuIndex.
@param[in] Cr3 The base address of the page tables to use when an SMI
is processed by the CPU specified by CpuIndex.
**/
VOID
EFIAPI
InstallSmiHandler (
IN UINTN CpuIndex,
IN UINT32 SmBase,
IN VOID *SmiStack,
IN UINTN StackSize,
IN UINTN GdtBase,
IN UINTN GdtSize,
IN UINTN IdtBase,
IN UINTN IdtSize,
IN UINT32 Cr3
)
{
if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {
//
// Install SMI handler provided by library
//
SmmCpuFeaturesInstallSmiHandler (
CpuIndex,
SmBase,
SmiStack,
StackSize,
GdtBase,
GdtSize,
IdtBase,
IdtSize,
Cr3
);
return;
}
//
// Initialize values in template before copy
//
gSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
gSmiCr3 = Cr3;
gSmbase = SmBase;
gSmiHandlerIdtr.Base = IdtBase;
gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);
//
// Set the value at the top of the CPU stack to the CPU Index
//
*(UINTN*)(UINTN)gSmiStack = CpuIndex;
//
// Copy template to CPU specific SMI handler location
//
CopyMem (
(VOID*)(UINTN)(SmBase + SMM_HANDLER_OFFSET),
(VOID*)gcSmiHandlerTemplate,
gcSmiHandlerSize
);
}

116
UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c Normal file
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@ -0,0 +1,116 @@
/** @file
SMM Timer feature support
Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "PiSmmCpuDxeSmm.h"
UINT64 mTimeoutTicker = 0;
//
// Number of counts in a roll-over cycle of the performance counter.
//
UINT64 mCycle = 0;
//
// Flag to indicate the performance counter is count-up or count-down.
//
BOOLEAN mCountDown;
/**
Initialize Timer for SMM AP Sync.
**/
VOID
InitializeSmmTimer (
VOID
)
{
UINT64 TimerFrequency;
UINT64 Start;
UINT64 End;
TimerFrequency = GetPerformanceCounterProperties (&Start, &End);
mTimeoutTicker = DivU64x32 (
MultU64x64(TimerFrequency, PcdGet64 (PcdCpuSmmApSyncTimeout)),
1000 * 1000
);
if (End < Start) {
mCountDown = TRUE;
mCycle = Start - End;
} else {
mCountDown = FALSE;
mCycle = End - Start;
}
}
/**
Start Timer for SMM AP Sync.
**/
UINT64
EFIAPI
StartSyncTimer (
VOID
)
{
return GetPerformanceCounter ();
}
/**
Check if the SMM AP Sync timer is timeout.
@param Timer The start timer from the begin.
**/
BOOLEAN
EFIAPI
IsSyncTimerTimeout (
IN UINT64 Timer
)
{
UINT64 CurrentTimer;
UINT64 Delta;
CurrentTimer = GetPerformanceCounter ();
//
// We need to consider the case that CurrentTimer is equal to Timer
// when some timer runs too slow and CPU runs fast. We think roll over
// condition does not happen on this case.
//
if (mCountDown) {
//
// The performance counter counts down. Check for roll over condition.
//
if (CurrentTimer <= Timer) {
Delta = Timer - CurrentTimer;
} else {
//
// Handle one roll-over.
//
Delta = mCycle - (CurrentTimer - Timer) + 1;
}
} else {
//
// The performance counter counts up. Check for roll over condition.
//
if (CurrentTimer >= Timer) {
Delta = CurrentTimer - Timer;
} else {
//
// Handle one roll-over.
//
Delta = mCycle - (Timer - CurrentTimer) + 1;
}
}
return (BOOLEAN) (Delta >= mTimeoutTicker);
}

102
UefiCpuPkg/UefiCpuPkg.dec
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@ -62,17 +62,76 @@
# 0x80000001 | Invalid value provided. # 0x80000001 | Invalid value provided.
# #
[PcdsFeatureFlag]
## Indicates if SMM Profile will be enabled.
# If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.
# This PCD is only for validation purpose. It should be set to false in production.<BR><BR>
# TRUE - SMM Profile will be enabled.<BR>
# FALSE - SMM Profile will be disabled.<BR>
# @Prompt Enable SMM Profile.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109
## Indicates if the SMM profile log buffer is a ring buffer.
# If disabled, no additional log can be done when the buffer is full.<BR><BR>
# TRUE - the SMM profile log buffer is a ring buffer.<BR>
# FALSE - the SMM profile log buffer is a normal buffer.<BR>
# @Prompt The SMM profile log buffer is a ring buffer.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a
## Indicates if SMM Startup AP in a blocking fashion.
# TRUE - SMM Startup AP in a blocking fashion.<BR>
# FALSE - SMM Startup AP in a non-blocking fashion.<BR>
# @Prompt SMM Startup AP in a blocking fashion.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108
## Indicates if SMM Stack Guard will be enabled.
# If enabled, stack overflow in SMM can be caught which eases debugging.<BR><BR>
# TRUE - SMM Stack Guard will be enabled.<BR>
# FALSE - SMM Stack Guard will be disabled.<BR>
# @Prompt Enable SMM Stack Guard.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE|BOOLEAN|0x1000001C
## Indicates if BSP election in SMM will be enabled.
# If enabled, a BSP will be dynamically elected among all processors in each SMI.
# Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>
# TRUE - BSP election in SMM will be enabled.<BR>
# FALSE - BSP election in SMM will be disabled.<BR>
# @Prompt Enable BSP election in SMM.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106
## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>
# TRUE - SMM CPU hot-plug will be enabled.<BR>
# FALSE - SMM CPU hot-plug will be disabled.<BR>
# @Prompt SMM CPU hot-plug.
gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C
## Indicates if SMM Debug will be enabled.
# If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>
# TRUE - SMM Debug will be enabled.<BR>
# FALSE - SMM Debug will be disabled.<BR>
# @Prompt Enable SMM Debug.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B
## Indicates if lock SMM Feature Control MSR.<BR><BR>
# TRUE - SMM Feature Control MSR will be locked.<BR>
# FALSE - SMM Feature Control MSR will not be locked.<BR>
# @Prompt Lock SMM Feature Control MSR.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B
[PcdsFixedAtBuild, PcdsPatchableInModule] [PcdsFixedAtBuild, PcdsPatchableInModule]
## This value is the CPU Local Apic base address, which aligns the address on a 4-KByte boundary. ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.
# @Prompt Configure base address of CPU Local Apic # @Prompt Configure base address of CPU Local APIC
# @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0 # @Expression 0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0
gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001 gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001
## Specifies delay value in microseconds after sending out an INIT IPI. ## Specifies delay value in microseconds after sending out an INIT IPI.
# @Prompt Configure delay value after send an INIT IPI # @Prompt Configure delay value after send an INIT IPI
gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002 gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002
## Specifies max supported number of Logical Processors. ## Specifies max supported number of Logical Processors.
# @Prompt Configure max supported number of Logical Processorss # @Prompt Configure max supported number of Logical Processors
gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002 gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002
## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must
## aligns the address on a 4-KByte boundary. ## aligns the address on a 4-KByte boundary.
# @Prompt Configure stack size for Application Processor (AP) # @Prompt Configure stack size for Application Processor (AP)
@ -82,6 +141,32 @@
# @Prompt Stack size in the temporary RAM. # @Prompt Stack size in the temporary RAM.
gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003 gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003
## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.
# @Prompt SMM profile data buffer size.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107
## Specifies stack size in bytes for each processor in SMM.
# @Prompt Processor stack size in SMM.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105
## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.
# @Prompt AP synchronization timeout value in SMM.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104
## Indicates if SMM Code Access Check is enabled.
# If enabled, the SMM handler cannot execute the code outside SMM regions.
# This PCD is suggested to TRUE in production image.<BR><BR>
# TRUE - SMM Code Access Check will be enabled.<BR>
# FALSE - SMM Code Access Check will be disabled.<BR>
# @Prompt SMM Code Access Check.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013
## Indicates the CPU synchronization method used when processing an SMI.
# 0x00 - Traditional CPU synchronization method.<BR>
# 0x01 - Relaxed CPU synchronization method.<BR>
# @Prompt SMM CPU Synchronization Method.
gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## Specifies timeout value in microseconds for the BSP to detect all APs for the first time. ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
# @Prompt Timeout for the BSP to detect all APs for the first time. # @Prompt Timeout for the BSP to detect all APs for the first time.
@ -93,5 +178,16 @@
# @Prompt Microcode Region size. # @Prompt Microcode Region size.
gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006 gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006
[PcdsDynamic, PcdsDynamicEx]
## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
# @Prompt The pointer to a CPU S3 data buffer.
# @ValidList 0x80000001 | 0
gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010
## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.
# @Prompt The pointer to CPU Hot Plug Data.
# @ValidList 0x80000001 | 0
gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011
[UserExtensions.TianoCore."ExtraFiles"] [UserExtensions.TianoCore."ExtraFiles"]
UefiCpuPkgExtra.uni UefiCpuPkgExtra.uni

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UefiCpuPkg/UefiCpuPkg.uni
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