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QuarkSocPkg: IntelQNCLib: remove set but unused variables

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This patch also removes a few PCI config space accesses, but that
shouldn't be a problem.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Kelly Steele <kelly.steele@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
This commit is contained in:
Laszlo Ersek 2016-03-18 21:22:02 +01:00
parent 025bf7bbde
commit 53632cea0c
1 changed files with 1 additions and 12 deletions
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13
QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c
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@ -403,9 +403,6 @@ PcieSetAspmAuto (
UINT32 EndpointPcieCapOffset; UINT32 EndpointPcieCapOffset;
UINT16 RootPortAspm; UINT16 RootPortAspm;
UINT16 EndPointAspm; UINT16 EndPointAspm;
UINT16 EndPointVendorId;
UINT16 EndPointDeviceId;
UINT8 EndPointRevId;
UINT16 AspmVal; UINT16 AspmVal;
UINT32 PortLxLat; UINT32 PortLxLat;
UINT32 EndPointLxLat; UINT32 EndPointLxLat;
@ -438,14 +435,10 @@ PcieSetAspmAuto (
EndPointAspm = (QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, (EndpointPcieCapOffset + PCIE_LINK_CAP_OFFSET)) & B_QNC_PCIE_LCAP_APMS_MASK) >> V_QNC_PCIE_LCAP_APMS_OFFSET; EndPointAspm = (QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, (EndpointPcieCapOffset + PCIE_LINK_CAP_OFFSET)) & B_QNC_PCIE_LCAP_APMS_MASK) >> V_QNC_PCIE_LCAP_APMS_OFFSET;
// //
// Mask APMC with values from lookup table. // TODO: Mask APMC with values from lookup table.
// RevID of 0xFF applies to all steppings. // RevID of 0xFF applies to all steppings.
// //
EndPointVendorId = QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, 0);
EndPointDeviceId = QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, 2);
EndPointRevId = QNCMmPci8 (0, EndpointBus, EndpointDevice, EndpointFunction, 8);
// TODO: Mask with latency/acceptable latency comparison results. // TODO: Mask with latency/acceptable latency comparison results.
AspmVal = RootPortAspm; AspmVal = RootPortAspm;
@ -585,7 +578,6 @@ QNCRootPortInit (
{ {
UINT64 RPBase; UINT64 RPBase;
UINT64 EndPointBase; UINT64 EndPointBase;
UINT64 LpcBase;
UINT16 AspmVal; UINT16 AspmVal;
UINT16 SlotStatus; UINT16 SlotStatus;
UINTN Index; UINTN Index;
@ -593,7 +585,6 @@ QNCRootPortInit (
UINT32 DwordReg; UINT32 DwordReg;
RPBase = PciExpressBar + (((PCI_BUS_NUMBER_QNC << 8) + ((PCI_DEVICE_NUMBER_PCIE_ROOTPORT) << 3) + ((PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 + RootPortIndex) << 0)) << 12); RPBase = PciExpressBar + (((PCI_BUS_NUMBER_QNC << 8) + ((PCI_DEVICE_NUMBER_PCIE_ROOTPORT) << 3) + ((PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 + RootPortIndex) << 0)) << 12);
LpcBase = PciExpressBar + (((PCI_BUS_NUMBER_QNC << 8) + (31 << 3) + (0 << 0)) << 12);
CapOffset = PcieFindCapId (PCI_BUS_NUMBER_QNC, (UINT8)(PCI_DEVICE_NUMBER_PCIE_ROOTPORT), (UINT8)(PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 + RootPortIndex), PCIE_CAPID); CapOffset = PcieFindCapId (PCI_BUS_NUMBER_QNC, (UINT8)(PCI_DEVICE_NUMBER_PCIE_ROOTPORT), (UINT8)(PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 + RootPortIndex), PCIE_CAPID);
if (CapOffset == 0) { if (CapOffset == 0) {
@ -906,7 +897,6 @@ PciExpressInit (
{ {
UINT64 PciExpressBar; UINT64 PciExpressBar;
UINT32 QNCRootComplexBar; UINT32 QNCRootComplexBar;
UINT32 QNCGpioBase;
UINT32 QNCPmioBase; UINT32 QNCPmioBase;
UINT32 QNCGpeBase; UINT32 QNCGpeBase;
UINTN RpEnableMask; UINTN RpEnableMask;
@ -917,7 +907,6 @@ PciExpressInit (
// Get BAR registers // Get BAR registers
// //
QNCRootComplexBar = QNC_RCRB_BASE; QNCRootComplexBar = QNC_RCRB_BASE;
QNCGpioBase = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
QNCPmioBase = LpcPciCfg32 (R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; QNCPmioBase = LpcPciCfg32 (R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK;
QNCGpeBase = LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & B_QNC_LPC_GPE0BLK_MASK; QNCGpeBase = LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & B_QNC_LPC_GPE0BLK_MASK;
RpEnableMask = 0; // assume all root ports are disabled RpEnableMask = 0; // assume all root ports are disabled