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Exchange the sequence of Asynchronous and Synchronous in CACHE_SRAM_TYPE_DATA according to SMBIOS specification.
Signed-off-by: lzeng14 Reviewed-by: li-elvin git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12871 6f19259b-4bc3-4df7-8a09-765794883524
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@ -857,8 +857,8 @@ typedef struct {
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UINT16 NonBurst :1;
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UINT16 Burst :1;
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UINT16 PipelineBurst :1;
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UINT16 Asynchronous :1;
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UINT16 Synchronous :1;
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UINT16 Asynchronous :1;
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UINT16 Reserved :9;
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} CACHE_SRAM_TYPE_DATA;
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