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ShellPkg: Fix pci command output of Max and Current Link Speed, and ASPM Support values to match PCIe Base Spec rev 3.0

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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Phillips <chrisp@hp.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>





git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14892 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Chris Phillips 2013-11-22 21:17:25 +00:00 committed by jcarsey
parent 416a423f08
commit 541ddf4436
2 changed files with 27 additions and 14 deletions
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38
ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
View File

@ -4051,32 +4051,41 @@ ExplainPcieLinkCap (
) )
{ {
UINT32 PcieLinkCap; UINT32 PcieLinkCap;
CHAR16 *SupLinkSpeeds; CHAR16 *MaxLinkSpeed;
CHAR16 *AspmValue; CHAR16 *AspmValue;
PcieLinkCap = PciExpressCap->LinkCap; PcieLinkCap = PciExpressCap->LinkCap;
switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap)) { switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap)) {
case 1: case 1:
SupLinkSpeeds = L"2.5 GT/s"; MaxLinkSpeed = L"2.5 GT/s";
break; break;
case 2: case 2:
SupLinkSpeeds = L"5.0 GT/s and 2.5 GT/s"; MaxLinkSpeed = L"5.0 GT/s";
break;
case 3:
MaxLinkSpeed = L"8.0 GT/s";
break; break;
default: default:
SupLinkSpeeds = L"Unknown"; MaxLinkSpeed = L"Unknown";
break; break;
} }
ShellPrintEx (-1, -1, ShellPrintEx (-1, -1,
L" Supported Link Speeds(3:0): %E%s supported%N\r\n", L" Maximum Link Speed(3:0): %E%s%N\r\n",
SupLinkSpeeds MaxLinkSpeed
); );
ShellPrintEx (-1, -1, ShellPrintEx (-1, -1,
L" Maximum Link Width(9:4): %Ex%d%N\r\n", L" Maximum Link Width(9:4): %Ex%d%N\r\n",
PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap) PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap)
); );
switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) { switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap)) {
case 0:
AspmValue = L"Not";
break;
case 1: case 1:
AspmValue = L"L0s Entry"; AspmValue = L"L0s";
break;
case 2:
AspmValue = L"L1";
break; break;
case 3: case 3:
AspmValue = L"L0s and L1"; AspmValue = L"L0s and L1";
@ -4204,23 +4213,26 @@ ExplainPcieLinkStatus (
) )
{ {
UINT16 PcieLinkStatus; UINT16 PcieLinkStatus;
CHAR16 *SupLinkSpeeds; CHAR16 *CurLinkSpeed;
PcieLinkStatus = PciExpressCap->LinkStatus; PcieLinkStatus = PciExpressCap->LinkStatus;
switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) { switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus)) {
case 1: case 1:
SupLinkSpeeds = L"2.5 GT/s"; CurLinkSpeed = L"2.5 GT/s";
break; break;
case 2: case 2:
SupLinkSpeeds = L"5.0 GT/s"; CurLinkSpeed = L"5.0 GT/s";
break;
case 3:
CurLinkSpeed = L"8.0 GT/s";
break; break;
default: default:
SupLinkSpeeds = L"Reserved"; CurLinkSpeed = L"Reserved";
break; break;
} }
ShellPrintEx (-1, -1, ShellPrintEx (-1, -1,
L" Current Link Speed(3:0): %E%s%N\r\n", L" Current Link Speed(3:0): %E%s%N\r\n",
SupLinkSpeeds CurLinkSpeed
); );
ShellPrintEx (-1, -1, ShellPrintEx (-1, -1,
L" Negotiated Link Width(9:4): %Ex%d%N\r\n", L" Negotiated Link Width(9:4): %Ex%d%N\r\n",

3
ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.h
View File

@ -1,6 +1,7 @@
/** @file /** @file
Header file for Pci shell Debug1 function. Header file for Pci shell Debug1 function.
Copyright (c) 2013 Hewlett-Packard Development Company, L.P.
Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR> Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -157,7 +158,7 @@ typedef enum {
// //
// Link Capabilities Register // Link Capabilities Register
// //
#define PCIE_CAP_SUP_LINK_SPEEDS(PcieLinkCap) \ #define PCIE_CAP_MAX_LINK_SPEED(PcieLinkCap) \
((PcieLinkCap) & 0x0f) ((PcieLinkCap) & 0x0f)
#define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \ #define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \
(((PcieLinkCap) >> 4) & 0x3f) (((PcieLinkCap) >> 4) & 0x3f)