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IntelFsp2Pkg: Fsp T new ARCH UPD Support 

Changes to support spec changes

1. Remove usage of Pcd.
2. Change code to validate the Temporary Ram size input.
3. Consume the input saved in YMM Register

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chiu Chasel <chasel.chiu@intel.com>
Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com>
Cc: Ni Ray <ray.ni@intel.com>

Signed-off-by: Duggapu Chinni B <chinni.b.duggapu@intel.com>
Reviewed-by: Chiu Chasel <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Duggapu Chinni B 2024-04-05 09:30:48 +05:30 committed by mergify[bot]
parent 932db9df0c
commit 543add1d41
14 changed files with 212 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf
View File

@ -60,6 +60,7 @@
FspSecPlatformLib
CpuLib
FspMultiPhaseLib
FspPlatformLib
[Pcd]
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES

1
IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
View File

@ -59,6 +59,7 @@
FspCommonLib
FspSecPlatformLib
CpuLib
FspPlatformLib
[Pcd]
gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES

1
IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm
View File

@ -11,7 +11,6 @@
; Following are fixed PCDs
;
extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))

1
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
View File

@ -11,7 +11,6 @@
; Following are fixed PCDs
;
extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))

60
IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
View File

@ -109,7 +109,8 @@ struc LoadMicrocodeParamsFsp24
.FsptArchReserved: resb 3
.FsptArchLength: resd 1
.FspDebugHandler resq 1
.FsptArchUpd: resd 4
.FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison is >= 3
.FsptArchUpd: resd 3
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resq 1
@ -267,7 +268,7 @@ ASM_PFX(LoadMicrocodeDefault):
cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader
cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
je Fsp24UpdHeader
jae Fsp24UpdHeader
jmp Fsp22UpdHeader
Fsp20UpdHeader:
@ -405,7 +406,7 @@ CheckAddress:
cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader1
cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
je Fsp24UpdHeader1;
jae Fsp24UpdHeader1;
jmp Fsp22UpdHeader1
Fsp20UpdHeader1:
@ -497,7 +498,8 @@ ASM_PFX(EstablishStackFsp):
; Enable FSP STACK
;
mov esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
add esp, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
LOAD_TEMPORARY_RAM_SIZE ecx
add esp, ecx
push DATA_LEN_OF_MCUD ; Size of the data region
push 4455434Dh ; Signature of the data region 'MCUD'
@ -506,7 +508,7 @@ ASM_PFX(EstablishStackFsp):
cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2
jb Fsp20UpdHeader2
cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2
je Fsp24UpdHeader2
jae Fsp24UpdHeader2
jmp Fsp22UpdHeader2
Fsp20UpdHeader2:
@ -554,12 +556,13 @@ ContinueAfterUpdPush:
;
; Set ECX/EDX to the BootLoader temporary memory range
;
mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
mov edx, ecx
add edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]
mov edx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
LOAD_TEMPORARY_RAM_SIZE ecx
add edx, ecx
sub edx, [ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))]
mov ecx, [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]
cmp ecx, edx ;If PcdFspReservedBufferSize >= PcdTemporaryRamSize, then error.
cmp ecx, edx ;If PcdFspReservedBufferSize >= TemporaryRamSize, then error.
jb EstablishStackFspSuccess
mov eax, 80000003h ;EFI_UNSUPPORTED
jmp EstablishStackFspExit
@ -599,6 +602,45 @@ ASM_PFX(TempRamInitApi):
CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
SAVE_ECX ; save UPD param to slot 3 in xmm6
mov edx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
mov edx, DWORD [edx]
;
; Read Fsp Arch2 revision
;
cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3
jb UseTemporaryRamSizePcd
;
; Read ARCH2 UPD input value.
;
mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize]
;
; As per spec, if Bootloader pass zero, use Fsp defined Size
;
cmp ebx, 0
jz UseTemporaryRamSizePcd
xor eax, eax
mov ax, WORD [esi + 020h] ; Read ImageAttribute
test ax, 16 ; check if Bit4 is set
jnz ConsumeInputConfiguration
;
; Sometimes user may change input value even if it is not supported
; return error if input is Non-Zero and not same as PcdTemporaryRamSize.
;
cmp ebx, edx
je UseTemporaryRamSizePcd
mov eax, 080000002h ; RETURN_INVALID_PARAMETER
jmp TempRamInitExit
ConsumeInputConfiguration:
;
; Read ARCH2 UPD value and Save.
;
SAVE_TEMPORARY_RAM_SIZE ebx
jmp GotTemporaryRamSize
UseTemporaryRamSizePcd:
SAVE_TEMPORARY_RAM_SIZE edx
GotTemporaryRamSize:
LOAD_ECX
;
; Sec Platform Init
;

11
IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
View File

@ -128,6 +128,17 @@
SXMMN xmm5, 1, eax
%endmacro
;
; XMM5 slot 2 for TemporaryRamSize
;
%macro LOAD_TEMPORARY_RAM_SIZE 1
LXMMN xmm5, %1, 2
%endmacro
%macro SAVE_TEMPORARY_RAM_SIZE 1
SXMMN xmm5, 2, %1
%endmacro
%macro ENABLE_SSE 0
;
; Initialize floating point units

9
IntelFsp2Pkg/FspSecCore/SecFsp.c
View File

@ -54,6 +54,7 @@ SecGetPlatformData (
UINT32 TopOfCar;
UINT32 *StackPtr;
UINT32 DwordSize;
UINT32 TemporaryRamSize;
FspPlatformData = &FspData->PlatformData;
@ -67,12 +68,20 @@ SecGetPlatformData (
FspPlatformData->MicrocodeRegionSize = 0;
FspPlatformData->CodeRegionBase = 0;
FspPlatformData->CodeRegionSize = 0;
TemporaryRamSize = 0;
//
// Pointer to the size field
//
TopOfCar = PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize);
StackPtr = (UINT32 *)(TopOfCar - sizeof (UINT32));
if ((*(StackPtr - 1) != FSP_MCUD_SIGNATURE) && (FspData->FspInfoHeader->ImageAttribute & BIT4)) {
ReadTemporaryRamSize (PcdGet32 (PcdTemporaryRamBase), &TemporaryRamSize);
if (TemporaryRamSize) {
TopOfCar = PcdGet32 (PcdTemporaryRamBase) + TemporaryRamSize;
StackPtr = (UINT32 *)(TopOfCar - sizeof (UINT32));
}
}
if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) {
while (*StackPtr != 0) {

1
IntelFsp2Pkg/FspSecCore/SecFsp.h
View File

@ -17,6 +17,7 @@
#include <Library/BaseMemoryLib.h>
#include <Library/FspCommonLib.h>
#include <Library/FspSecPlatformLib.h>
#include <Library/FspPlatformLib.h>
#define FSP_MCUD_SIGNATURE SIGNATURE_32 ('M', 'C', 'U', 'D')
#define FSP_PER0_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', '0')

67
IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
View File

@ -76,7 +76,8 @@ struc LoadMicrocodeParamsFsp24
.FsptArchReserved: resb 3
.FsptArchLength: resd 1
.FspDebugHandler resq 1
.FsptArchUpd: resd 4
.FspTemporaryRamSize: resd 1 ; Supported only if ArchRevison is >= 3
.FsptArchUpd: resd 3
; }
; FSPT_CORE_UPD {
.MicrocodeCodeAddr: resq 1
@ -163,7 +164,7 @@ ASM_PFX(LoadMicrocodeDefault):
cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2
jb ParamError
cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2
jne ParamError
jb ParamError
; UPD structure is compliant with FSP spec 2.4
mov rax, qword [rsp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize]
@ -273,7 +274,7 @@ CheckAddress:
cmp byte [rsp + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2
jb ParamError
cmp byte [rsp + LoadMicrocodeParamsFsp24.FsptArchRevision], 2
jne ParamError
jb ParamError
; UPD structure is compliant with FSP spec 2.4
; Is automatic size detection ?
@ -337,8 +338,8 @@ ASM_PFX(EstablishStackFsp):
;
mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
mov esp, DWORD[rax]
mov rax, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
add esp, DWORD[rax]
LOAD_TEMPORARY_RAM_SIZE rax
add esp, eax
sub esp, 4
mov dword[esp], DATA_LEN_OF_MCUD ; Size of the data region
@ -349,7 +350,7 @@ ASM_PFX(EstablishStackFsp):
cmp byte [rdx + LoadMicrocodeParamsFsp24.FspUpdHeaderRevision], 2
jb ParamError1
cmp byte [rdx + LoadMicrocodeParamsFsp24.FsptArchRevision], 2
je Fsp24UpdHeader
jnb Fsp24UpdHeader
ParamError1:
mov rax, 08000000000000002h
@ -397,8 +398,8 @@ ContinueAfterUpdPush:
;
mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
mov edx, [ecx]
mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
add edx, [ecx]
LOAD_TEMPORARY_RAM_SIZE rcx
add edx, ecx
mov rcx, ASM_PFX(PcdGet32 (PcdFspReservedBufferSize))
sub edx, [ecx]
mov rcx, ASM_PFX(PcdGet32 (PcdTemporaryRamBase))
@ -439,6 +440,14 @@ ASM_PFX(TempRamInitApi):
;
SAVE_BFV rbp
;
; Save timestamp into YMM6
;
rdtsc
shl rdx, 32
or rax, rdx
SAVE_TS rax
;
; Save Input Parameter in YMM10
;
@ -455,14 +464,46 @@ ASM_PFX(TempRamInitApi):
ParamValid:
SAVE_RCX
mov rdx, ASM_PFX(PcdGet32 (PcdTemporaryRamSize))
mov edx, DWORD [rdx]
;
; Save timestamp into YMM6
; Read Fsp Arch2 revision
;
rdtsc
shl rdx, 32
or rax, rdx
SAVE_TS rax
cmp byte [ecx + LoadMicrocodeParamsFsp24.FsptArchRevision], 3
jb UseTemporaryRamSizePcd
;
; Read ARCH2 UPD input value.
;
mov ebx, DWORD [ecx + LoadMicrocodeParamsFsp24.FspTemporaryRamSize]
;
; As per spec, if Bootloader pass zero, use Fsp defined Size
;
cmp ebx, 0
jz UseTemporaryRamSizePcd
xor rax, rax
mov ax, WORD [rsi + 020h] ; Read ImageAttribute
test ax, 16 ; check if Bit4 is set
jnz ConsumeInputConfiguration
;
; Sometimes user may change input value even if it is not supported
; return error if input is Non-Zero and not same as PcdTemporaryRamSize.
;
cmp ebx, edx
je UseTemporaryRamSizePcd
mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETER
jmp TempRamInitExit
ConsumeInputConfiguration:
;
; Read ARCH2 UPD value and Save.
; Only low-32 bits of rbx/rdx holds the temporary ram size.
;
SAVE_TEMPORARY_RAM_SIZE rbx
jmp GotTemporaryRamSize
UseTemporaryRamSizePcd:
SAVE_TEMPORARY_RAM_SIZE rdx
GotTemporaryRamSize:
;
; Sec Platform Init
;

12
IntelFsp2Pkg/Include/FspEas/FspApi.h
View File

@ -139,7 +139,7 @@ typedef struct {
///
typedef struct {
///
/// Revision of the structure is 2 for this version of the specification.
/// Revision of the structure is 3 for this version of the specification.
///
UINT8 Revision;
UINT8 Reserved[3];
@ -152,7 +152,15 @@ typedef struct {
/// occurring during FSP execution.
///
EFI_PHYSICAL_ADDRESS FspDebugHandler;
UINT8 Reserved1[16];
///
/// FspTemporaryRamSize is Optional & valid only when
/// FSP image attribute (BIT4) is set. If Programmed as Zero, Platform
/// recommended value will be used, otherwise input value will be used
/// to configure TemporaryRamSize. Refer FSP Integration guide for valid
/// TemporaryRamSize range for each platform.
///
UINT32 FspTemporaryRamSize;
UINT8 Reserved1[12];
} FSPT_ARCH2_UPD;
///

13
IntelFsp2Pkg/Include/Library/FspPlatformLib.h
View File

@ -121,4 +121,17 @@ FspTempRamExitDone2 (
IN EFI_STATUS Status
);
/**
Calculate TemporaryRam Size using Base address.
@param[in] TemporaryRamBase the address of target memory
@param[out] TemporaryRamSize the size of target memory
**/
VOID
EFIAPI
ReadTemporaryRamSize (
IN UINT32 TemporaryRamBase,
OUT UINT32 *TemporaryRamSize
);
#endif

21
IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc
View File

@ -201,6 +201,27 @@
movq rcx, xmm5
%endmacro
;
; Save TemporaryRamSize to YMM10[192:255]
; arg 1:general purpose register which holds TemporaryRamSize
; Modified: XMM5 and YMM10[192:255]
;
%macro SAVE_TEMPORARY_RAM_SIZE 1
LYMMN ymm10, xmm5, 1
SXMMN xmm5, 1, %1
SYMMN ymm10, 1, xmm5
%endmacro
;
; Restore TemporaryRamSize from YMM10[192:255]
; arg 1:general purpose register where to save TemporaryRamSize
; Modified: XMM5 and %1
;
%macro LOAD_TEMPORARY_RAM_SIZE 1
LYMMN ymm10, xmm5, 1
LXMMN xmm5, %1, 1
%endmacro
;
; YMM7[128:191] for calling stack
; arg 1:Entry

4
IntelFsp2Pkg/IntelFsp2Pkg.dsc
View File

@ -46,9 +46,9 @@
FspSecPlatformLib|IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.inf
FspMultiPhaseLib|IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf
[LibraryClasses.common.PEIM]
[LibraryClasses.common.PEIM, LibraryClasses.common.SEC]
PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf

38
IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformMemory.c
View File

@ -6,6 +6,7 @@
**/
#include <PiPei.h>
#include <Register/Intel/Msr.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
@ -119,3 +120,40 @@ FspGetSystemMemorySize (
Hob.Raw = GET_NEXT_HOB (Hob);
}
}
/**
Calculate TemporaryRam Size using Base address.
@param[in] TemporaryRamBase the address of target memory
@param[out] TemporaryRamSize the size of target memory
**/
VOID
EFIAPI
ReadTemporaryRamSize (
IN UINT32 TemporaryRamBase,
OUT UINT32 *TemporaryRamSize
)
{
MSR_IA32_MTRRCAP_REGISTER Msr;
UINT32 MsrNum;
UINT32 MsrNumEnd;
if (TemporaryRamBase == 0) {
return;
}
*TemporaryRamSize = 0;
Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
MsrNumEnd = MSR_IA32_MTRR_PHYSBASE0 + (2 * (Msr.Bits.VCNT));
for (MsrNum = MSR_IA32_MTRR_PHYSBASE0; MsrNum < MsrNumEnd; MsrNum += 2) {
if ((AsmReadMsr64 (MsrNum+1) & BIT11) != 0 ) {
if (TemporaryRamBase == (AsmReadMsr64 (MsrNum) & 0xFFFFF000)) {
*TemporaryRamSize = (~(AsmReadMsr64 (MsrNum + 1) & 0xFFFFF000) + 1);
break;
}
}
}
return;
}