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Syncing GCC and ARMASM assembly. Made chunks of the ARMASM lowercase to make the diff easier. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10163 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-03-03 04:14:16 +00:00
parent c029854f20
commit 548af3e780
2 changed files with 111 additions and 110 deletions
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18
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
View File

@ -12,8 +12,6 @@
# #
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
.text
.align 2
.globl ASM_PFX(ArmInvalidateInstructionCache) .globl ASM_PFX(ArmInvalidateInstructionCache)
.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA) .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
.globl ASM_PFX(ArmCleanDataCacheEntryByMVA) .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
@ -29,8 +27,6 @@
.globl ASM_PFX(ArmDisableDataCache) .globl ASM_PFX(ArmDisableDataCache)
.globl ASM_PFX(ArmEnableInstructionCache) .globl ASM_PFX(ArmEnableInstructionCache)
.globl ASM_PFX(ArmDisableInstructionCache) .globl ASM_PFX(ArmDisableInstructionCache)
.globl ASM_PFX(ArmEnableExtendPTConfig)
.globl ASM_PFX(ArmDisableExtendPTConfig)
.globl ASM_PFX(ArmEnableBranchPrediction) .globl ASM_PFX(ArmEnableBranchPrediction)
.globl ASM_PFX(ArmDisableBranchPrediction) .globl ASM_PFX(ArmDisableBranchPrediction)
.globl ASM_PFX(ArmV7AllDataCachesOperation) .globl ASM_PFX(ArmV7AllDataCachesOperation)
@ -38,6 +34,8 @@
.globl ASM_PFX(ArmDataSyncronizationBarrier) .globl ASM_PFX(ArmDataSyncronizationBarrier)
.globl ASM_PFX(ArmInstructionSynchronizationBarrier) .globl ASM_PFX(ArmInstructionSynchronizationBarrier)
.text
.align 2
.set DC_ON, (0x1<<2) .set DC_ON, (0x1<<2)
.set IC_ON, (0x1<<12) .set IC_ON, (0x1<<12)
@ -104,11 +102,14 @@ ASM_PFX(ArmEnableMmu):
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
orr R0,R0,#1 orr R0,R0,#1
mcr p15,0,R0,c1,c0,0 mcr p15,0,R0,c1,c0,0
dsb
isb
bx LR bx LR
ASM_PFX(ArmMmuEnabled): ASM_PFX(ArmMmuEnabled):
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
and R0,R0,#1 and R0,R0,#1
isb
bx LR bx LR
@ -118,7 +119,6 @@ ASM_PFX(ArmDisableMmu):
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
bic R0,R0,#1 bic R0,R0,#1
mcr p15,0,R0,c1,c0,0 @Disable MMU mcr p15,0,R0,c1,c0,0 @Disable MMU
mov R0,#0
dsb dsb
isb isb
bx LR bx LR
@ -192,14 +192,16 @@ Loop1:
cmp R12, #2 cmp R12, #2
blt L_Skip @ no cache or only instruction cache at this level blt L_Skip @ no cache or only instruction cache at this level
mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
isb @ ISB to sync the change to the CacheSizeID reg isb @ isb to sync the change to the CacheSizeID reg
mcr p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
and R2, R12, #0x7 @ extract the line length field and R2, R12, #0x7 @ extract the line length field
and R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
@ ldr R4, =0x3FF
mov R4, #0x400 mov R4, #0x400
sub R4, R4, #1 sub R4, R4, #1
ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned) ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
clz R5, R4 @ R5 is the bit position of the way size increment clz R5, R4 @ R5 is the bit position of the way size increment
@ ldr R7, =0x00007FFF
mov R7, #0x00008000 mov R7, #0x00008000
sub R7, R7, #1 sub R7, R7, #1
ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned) ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)

203
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -34,85 +34,83 @@
EXPORT ArmDataSyncronizationBarrier EXPORT ArmDataSyncronizationBarrier
EXPORT ArmInstructionSynchronizationBarrier EXPORT ArmInstructionSynchronizationBarrier
AREA ArmCacheLib, CODE, READONLY
PRESERVE8
DC_ON EQU ( 0x1:SHL:2 ) DC_ON EQU ( 0x1:SHL:2 )
IC_ON EQU ( 0x1:SHL:12 ) IC_ON EQU ( 0x1:SHL:12 )
AREA ArmCacheLib, CODE, READONLY
PRESERVE8
ArmInvalidateDataCacheEntryByMVA ArmInvalidateDataCacheEntryByMVA
MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
DSB dsb
ISB isb
BX lr bx lr
ArmCleanDataCacheEntryByMVA ArmCleanDataCacheEntryByMVA
MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
DSB dsb
ISB isb
BX lr bx lr
ArmCleanInvalidateDataCacheEntryByMVA ArmCleanInvalidateDataCacheEntryByMVA
MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
DSB dsb
ISB isb
BX lr bx lr
ArmInvalidateDataCacheEntryBySetWay ArmInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
DSB dsb
ISB isb
bx lr bx lr
ArmCleanInvalidateDataCacheEntryBySetWay ArmCleanInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
DSB dsb
ISB isb
bx lr bx lr
ArmCleanDataCacheEntryBySetWay ArmCleanDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c10, 2 ; Clean this line mcr p15, 0, r0, c7, c10, 2 ; Clean this line
DSB dsb
ISB isb
bx lr bx lr
ArmDrainWriteBuffer ArmDrainWriteBuffer
mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
DSB dsb
ISB isb
bx lr bx lr
ArmInvalidateInstructionCache ArmInvalidateInstructionCache
MOV R0,#0 mov R0,#0
MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
MOV R0,#0 mov R0,#0
MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier dsb
DSB isb
ISB bx LR
BX LR
ArmEnableMmu ArmEnableMmu
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
orr R0,R0,#1 orr R0,R0,#1
mcr p15,0,R0,c1,c0,0 mcr p15,0,R0,c1,c0,0
DSB dsb
ISB isb
bx LR bx LR
ArmMmuEnabled ArmMmuEnabled
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
and R0,R0,#1 and R0,R0,#1
ISB isb
bx LR bx LR
ArmDisableMmu ArmDisableMmu
@ -121,117 +119,118 @@ ArmDisableMmu
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
bic R0,R0,#1 bic R0,R0,#1
mcr p15,0,R0,c1,c0,0 ;Disable MMU mcr p15,0,R0,c1,c0,0 ;Disable MMU
DSB dsb
ISB isb
bx LR bx LR
ArmEnableDataCache ArmEnableDataCache
LDR R1,=DC_ON ldr R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set C bit orr R0,R0,R1 ;Set C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
DSB dsb
ISB isb
BX LR bx LR
ArmDisableDataCache ArmDisableDataCache
LDR R1,=DC_ON ldr R1,=DC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear C bit bic R0,R0,R1 ;Clear C bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
ISB isb
BX LR bx LR
ArmEnableInstructionCache ArmEnableInstructionCache
LDR R1,=IC_ON ldr R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
ORR R0,R0,R1 ;Set I bit orr R0,R0,R1 ;Set I bit
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
ISB dsb
BX LR isb
bx LR
ArmDisableInstructionCache ArmDisableInstructionCache
LDR R1,=IC_ON ldr R1,=IC_ON
MRC p15,0,R0,c1,c0,0 ;Read control register configuration data mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit. BIC R0,R0,R1 ;Clear I bit.
MCR p15,0,r0,c1,c0,0 ;Write control register configuration data mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
ISB isb
BX LR bx LR
ArmEnableBranchPrediction ArmEnableBranchPrediction
mrc p15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #0x00000800 orr r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
ISB isb
bx LR bx LR
ArmDisableBranchPrediction ArmDisableBranchPrediction
mrc p15, 0, r0, c1, c0, 0 mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00000800 bic r0, r0, #0x00000800
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
ISB isb
bx LR bx LR
ArmV7AllDataCachesOperation ArmV7AllDataCachesOperation
STMFD SP!,{r4-r12, LR} stmfd SP!,{r4-r12, LR}
MOV R1, R0 ; Save Function call in R1 mov R1, R0 ; Save Function call in R1
MRC p15, 1, R6, c0, c0, 1 ; Read CLIDR mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
ANDS R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC) ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
MOV R3, R3, LSR #23 ; Cache level value (naturally aligned) mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
BEQ Finished beq Finished
MOV R10, #0 mov R10, #0
Loop1 Loop1
ADD R2, R10, R10, LSR #1 ; Work out 3xcachelevel add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
MOV R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
AND R12, R12, #7 ; get those 3 bits alone and R12, R12, #7 ; get those 3 bits alone
CMP R12, #2 cmp R12, #2
BLT Skip ; no cache or only instruction cache at this level blt Skip ; no cache or only instruction cache at this level
MCR p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
ISB ; ISB to sync the change to the CacheSizeID reg isb ; isb to sync the change to the CacheSizeID reg
MRC p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR) mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
AND R2, R12, #&7 ; extract the line length field and R2, R12, #&7 ; extract the line length field
ADD R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes) add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
LDR R4, =0x3FF ldr R4, =0x3FF
ANDS R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned) ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
CLZ R5, R4 ; R5 is the bit position of the way size increment clz R5, R4 ; R5 is the bit position of the way size increment
LDR R7, =0x00007FFF ldr R7, =0x00007FFF
ANDS R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned) ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
Loop2 Loop2
MOV R9, R4 ; R9 working copy of the max way size (right aligned) mov R9, R4 ; R9 working copy of the max way size (right aligned)
Loop3 Loop3
ORR R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
ORR R0, R0, R7, LSL R2 ; factor in the index number orr R0, R0, R7, LSL R2 ; factor in the index number
BLX R1 blx R1
SUBS R9, R9, #1 ; decrement the way number subs R9, R9, #1 ; decrement the way number
BGE Loop3 bge Loop3
SUBS R7, R7, #1 ; decrement the index subs R7, R7, #1 ; decrement the index
BGE Loop2 bge Loop2
Skip Skip
ADD R10, R10, #2 ; increment the cache number add R10, R10, #2 ; increment the cache number
CMP R3, R10 cmp R3, R10
BGT Loop1 bgt Loop1
Finished Finished
LDMFD SP!, {r4-r12, lr} ldmfd SP!, {r4-r12, lr}
BX LR bx LR
ArmDataMemoryBarrier ArmDataMemoryBarrier
DMB dmb
BX LR bx LR
ArmDataSyncronizationBarrier ArmDataSyncronizationBarrier
DSB dsb
BX LR bx LR
ArmInstructionSynchronizationBarrier ArmInstructionSynchronizationBarrier
ISB isb
BX LR bx LR
END END