mirror of https://github.com/acidanthera/audk.git
Syncing GCC and ARMASM assembly. Made chunks of the ARMASM lowercase to make the diff easier.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10163 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish
parent
c029854f20
commit
548af3e780
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@ -12,8 +12,6 @@
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#
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#------------------------------------------------------------------------------
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.text
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.align 2
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.globl ASM_PFX(ArmInvalidateInstructionCache)
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.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
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.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
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@ -29,8 +27,6 @@
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.globl ASM_PFX(ArmDisableDataCache)
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.globl ASM_PFX(ArmEnableInstructionCache)
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.globl ASM_PFX(ArmDisableInstructionCache)
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.globl ASM_PFX(ArmEnableExtendPTConfig)
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.globl ASM_PFX(ArmDisableExtendPTConfig)
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.globl ASM_PFX(ArmEnableBranchPrediction)
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.globl ASM_PFX(ArmDisableBranchPrediction)
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.globl ASM_PFX(ArmV7AllDataCachesOperation)
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@ -38,6 +34,8 @@
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.globl ASM_PFX(ArmDataSyncronizationBarrier)
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.globl ASM_PFX(ArmInstructionSynchronizationBarrier)
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.text
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.align 2
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.set DC_ON, (0x1<<2)
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.set IC_ON, (0x1<<12)
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@ -104,11 +102,14 @@ ASM_PFX(ArmEnableMmu):
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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dsb
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isb
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bx LR
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ASM_PFX(ArmMmuEnabled):
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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isb
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bx LR
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@ -118,7 +119,6 @@ ASM_PFX(ArmDisableMmu):
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0 @Disable MMU
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mov R0,#0
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dsb
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isb
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bx LR
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@ -192,14 +192,16 @@ Loop1:
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cmp R12, #2
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blt L_Skip @ no cache or only instruction cache at this level
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mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
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isb @ ISB to sync the change to the CacheSizeID reg
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mcr p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
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isb @ isb to sync the change to the CacheSizeID reg
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mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
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and R2, R12, #0x7 @ extract the line length field
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and R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
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add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
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@ ldr R4, =0x3FF
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mov R4, #0x400
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sub R4, R4, #1
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ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
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clz R5, R4 @ R5 is the bit position of the way size increment
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@ ldr R7, =0x00007FFF
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mov R7, #0x00008000
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sub R7, R7, #1
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ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
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@ -34,85 +34,83 @@
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EXPORT ArmDataSyncronizationBarrier
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EXPORT ArmInstructionSynchronizationBarrier
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AREA ArmCacheLib, CODE, READONLY
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PRESERVE8
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DC_ON EQU ( 0x1:SHL:2 )
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IC_ON EQU ( 0x1:SHL:12 )
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AREA ArmCacheLib, CODE, READONLY
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PRESERVE8
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ArmInvalidateDataCacheEntryByMVA
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MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
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DSB
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ISB
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BX lr
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mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
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dsb
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isb
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bx lr
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ArmCleanDataCacheEntryByMVA
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MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
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DSB
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ISB
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BX lr
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mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
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dsb
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isb
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bx lr
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ArmCleanInvalidateDataCacheEntryByMVA
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MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
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DSB
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ISB
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BX lr
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mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
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dsb
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isb
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bx lr
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ArmInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
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DSB
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ISB
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dsb
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isb
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bx lr
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ArmCleanInvalidateDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
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DSB
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ISB
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dsb
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isb
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bx lr
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ArmCleanDataCacheEntryBySetWay
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mcr p15, 0, r0, c7, c10, 2 ; Clean this line
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DSB
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ISB
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dsb
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isb
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bx lr
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ArmDrainWriteBuffer
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mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
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DSB
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ISB
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dsb
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isb
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bx lr
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ArmInvalidateInstructionCache
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MOV R0,#0
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MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
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MOV R0,#0
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MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
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DSB
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ISB
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BX LR
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mov R0,#0
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mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
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mov R0,#0
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dsb
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isb
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bx LR
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ArmEnableMmu
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mrc p15,0,R0,c1,c0,0
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orr R0,R0,#1
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mcr p15,0,R0,c1,c0,0
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DSB
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ISB
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dsb
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isb
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bx LR
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ArmMmuEnabled
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mrc p15,0,R0,c1,c0,0
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and R0,R0,#1
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ISB
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isb
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bx LR
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ArmDisableMmu
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@ -121,117 +119,118 @@ ArmDisableMmu
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mrc p15,0,R0,c1,c0,0
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bic R0,R0,#1
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mcr p15,0,R0,c1,c0,0 ;Disable MMU
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DSB
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ISB
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dsb
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isb
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bx LR
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ArmEnableDataCache
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LDR R1,=DC_ON
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MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
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ORR R0,R0,R1 ;Set C bit
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MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
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DSB
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ISB
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BX LR
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
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orr R0,R0,R1 ;Set C bit
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mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
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dsb
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isb
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bx LR
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ArmDisableDataCache
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LDR R1,=DC_ON
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MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
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BIC R0,R0,R1 ;Clear C bit
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MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
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ISB
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BX LR
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ldr R1,=DC_ON
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mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
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bic R0,R0,R1 ;Clear C bit
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mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
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isb
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bx LR
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ArmEnableInstructionCache
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LDR R1,=IC_ON
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MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
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ORR R0,R0,R1 ;Set I bit
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MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
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ISB
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BX LR
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
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orr R0,R0,R1 ;Set I bit
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mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
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dsb
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isb
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bx LR
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ArmDisableInstructionCache
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LDR R1,=IC_ON
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MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
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ldr R1,=IC_ON
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mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
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BIC R0,R0,R1 ;Clear I bit.
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MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
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ISB
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BX LR
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mcr p15,0,r0,c1,c0,0 ;Write control register configuration data
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isb
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bx LR
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ArmEnableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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ISB
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isb
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bx LR
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ArmDisableBranchPrediction
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00000800
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mcr p15, 0, r0, c1, c0, 0
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ISB
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isb
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bx LR
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ArmV7AllDataCachesOperation
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STMFD SP!,{r4-r12, LR}
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MOV R1, R0 ; Save Function call in R1
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MRC p15, 1, R6, c0, c0, 1 ; Read CLIDR
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ANDS R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
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MOV R3, R3, LSR #23 ; Cache level value (naturally aligned)
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BEQ Finished
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MOV R10, #0
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stmfd SP!,{r4-r12, LR}
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mov R1, R0 ; Save Function call in R1
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mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
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ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
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mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
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beq Finished
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mov R10, #0
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Loop1
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ADD R2, R10, R10, LSR #1 ; Work out 3xcachelevel
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MOV R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
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AND R12, R12, #7 ; get those 3 bits alone
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CMP R12, #2
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BLT Skip ; no cache or only instruction cache at this level
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MCR p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
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ISB ; ISB to sync the change to the CacheSizeID reg
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MRC p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
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AND R2, R12, #&7 ; extract the line length field
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ADD R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
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LDR R4, =0x3FF
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ANDS R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
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CLZ R5, R4 ; R5 is the bit position of the way size increment
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LDR R7, =0x00007FFF
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ANDS R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
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add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
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mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
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and R12, R12, #7 ; get those 3 bits alone
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cmp R12, #2
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blt Skip ; no cache or only instruction cache at this level
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mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
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isb ; isb to sync the change to the CacheSizeID reg
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mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
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and R2, R12, #&7 ; extract the line length field
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add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
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ldr R4, =0x3FF
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ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
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clz R5, R4 ; R5 is the bit position of the way size increment
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ldr R7, =0x00007FFF
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ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
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Loop2
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MOV R9, R4 ; R9 working copy of the max way size (right aligned)
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mov R9, R4 ; R9 working copy of the max way size (right aligned)
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Loop3
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ORR R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
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ORR R0, R0, R7, LSL R2 ; factor in the index number
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orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
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orr R0, R0, R7, LSL R2 ; factor in the index number
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BLX R1
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blx R1
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SUBS R9, R9, #1 ; decrement the way number
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BGE Loop3
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SUBS R7, R7, #1 ; decrement the index
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BGE Loop2
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subs R9, R9, #1 ; decrement the way number
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bge Loop3
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subs R7, R7, #1 ; decrement the index
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bge Loop2
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Skip
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ADD R10, R10, #2 ; increment the cache number
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CMP R3, R10
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BGT Loop1
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add R10, R10, #2 ; increment the cache number
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cmp R3, R10
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bgt Loop1
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Finished
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LDMFD SP!, {r4-r12, lr}
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BX LR
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ldmfd SP!, {r4-r12, lr}
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bx LR
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ArmDataMemoryBarrier
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DMB
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BX LR
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dmb
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bx LR
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ArmDataSyncronizationBarrier
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DSB
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BX LR
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dsb
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bx LR
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ArmInstructionSynchronizationBarrier
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ISB
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BX LR
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isb
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bx LR
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END
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