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UefiCpuPkg: Backup and Restore MSR IA32_U_CET in SMI handler. 

OS may enable CET-IBT feature by set MSR IA32_U_CET.bit2.
If IA32_U_CET.bit2 is set, CPU is in WAIT_FOR_ENDBRANCH state and
 the next assemble code is not ENDBR, it will trigger #CP exception
 when set CR4.CET bit.
SMI handler needs to backup MSR IA32_U_CET and clear MSR IA32_U_CET
 before set CR4.CET bit,
And SMI handler needs to restore MSR IA32_U_CET when exit SMI handler.

Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Cc: Tan Dun <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
This commit is contained in:
Sheng Wei 2023-11-09 17:14:39 +08:00 committed by mergify[bot]
parent fd1dd8568c
commit 553dfb0f57
2 changed files with 30 additions and 0 deletions
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15
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
View File

@ -202,11 +202,21 @@ ASM_PFX(mPatchCetSupported):
push edx push edx
push eax push eax
mov ecx, MSR_IA32_U_CET
rdmsr
push edx
push eax
mov ecx, MSR_IA32_PL0_SSP mov ecx, MSR_IA32_PL0_SSP
rdmsr rdmsr
push edx push edx
push eax push eax
mov ecx, MSR_IA32_U_CET
xor eax, eax
xor edx, edx
wrmsr
mov ecx, MSR_IA32_S_CET mov ecx, MSR_IA32_S_CET
mov eax, MSR_IA32_CET_SH_STK_EN mov eax, MSR_IA32_CET_SH_STK_EN
xor edx, edx xor edx, edx
@ -276,6 +286,11 @@ CetDone:
pop edx pop edx
wrmsr wrmsr
mov ecx, MSR_IA32_U_CET
pop eax
pop edx
wrmsr
mov ecx, MSR_IA32_S_CET mov ecx, MSR_IA32_S_CET
pop eax pop eax
pop edx pop edx

15
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
View File

@ -217,6 +217,11 @@ ASM_PFX(mPatchCetSupported):
push rdx push rdx
push rax push rax
mov ecx, MSR_IA32_U_CET
rdmsr
push rdx
push rax
mov ecx, MSR_IA32_PL0_SSP mov ecx, MSR_IA32_PL0_SSP
rdmsr rdmsr
push rdx push rdx
@ -227,6 +232,11 @@ ASM_PFX(mPatchCetSupported):
push rdx push rdx
push rax push rax
mov ecx, MSR_IA32_U_CET
xor eax, eax
xor edx, edx
wrmsr
mov ecx, MSR_IA32_S_CET mov ecx, MSR_IA32_S_CET
mov eax, MSR_IA32_CET_SH_STK_EN mov eax, MSR_IA32_CET_SH_STK_EN
xor edx, edx xor edx, edx
@ -325,6 +335,11 @@ mCetSupportedAbsAddr:
pop rdx pop rdx
wrmsr wrmsr
mov ecx, MSR_IA32_U_CET
pop rax
pop rdx
wrmsr
mov ecx, MSR_IA32_S_CET mov ecx, MSR_IA32_S_CET
pop rax pop rax
pop rdx pop rdx