tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ArmPkg: Renamed library 'PL390GicLib' into 'ArmGicLib' 

This library is the interface for the ARM Generic Interrupt Controller
Architecture Specification.
ARM Platform can use any GIC controller (not necessary PL390 GIC).




git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12411 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-09-22 22:59:52 +00:00
parent 75e4db2d3b
commit 55a0d64b88
21 changed files with 292 additions and 327 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
ArmPkg/ArmPkg.dsc
View File

@ -120,6 +120,7 @@
ArmPkg/Drivers/CpuDxe/CpuDxe.inf ArmPkg/Drivers/CpuDxe/CpuDxe.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf ArmPkg/Drivers/CpuPei/CpuPei.inf
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmPkg/Drivers/PL390Gic/PL390GicSec.inf ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf ArmPkg/Filesystem/SemihostFs/SemihostFs.inf

71
ArmPkg/Drivers/PL390Gic/PL390Gic.c Normal file
View File

@ -0,0 +1,71 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <Uefi.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
VOID
EFIAPI
ArmGicSendSgiTo (
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList
)
{
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
}
UINT32
EFIAPI
ArmGicAcknowledgeSgiFrom (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId
)
{
INTN InterruptId;
InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
}
}
UINT32
EFIAPI
ArmGicAcknowledgeSgi2From (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId,
IN INTN SgiId
)
{
INTN InterruptId;
InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
}
}

46
ArmPkg/Drivers/PL390Gic/PL390GicDxe.c
View File

@ -29,25 +29,24 @@ Abstract:
#include <Library/UefiLib.h> #include <Library/UefiLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
#include <Protocol/Cpu.h> #include <Protocol/Cpu.h>
#include <Protocol/HardwareInterrupt.h> #include <Protocol/HardwareInterrupt.h>
#include <Drivers/PL390Gic.h>
// number of 32-bit registers needed to represent those interrupts as a bit // number of 32-bit registers needed to represent those interrupts as a bit
// (used for enable set, enable clear, pending set, pending clear, and active regs) // (used for enable set, enable clear, pending set, pending clear, and active regs)
#define GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32) #define ARM_GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32)
// number of 32-bit registers needed to represent those interrupts as two bits // number of 32-bit registers needed to represent those interrupts as two bits
// (used for configuration reg) // (used for configuration reg)
#define GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16) #define ARM_GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16)
// number of 32-bit registers needed to represent interrupts as 8-bit priority field // number of 32-bit registers needed to represent interrupts as 8-bit priority field
// (used for priority regs) // (used for priority regs)
#define GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4) #define ARM_GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4)
#define GIC_DEFAULT_PRIORITY 0x80 #define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol; extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
@ -130,7 +129,7 @@ EnableInterruptSource (
RegShift = Source % 32; RegShift = Source % 32;
// write set-enable register // write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset), 1 << RegShift); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -165,7 +164,7 @@ DisableInterruptSource (
RegShift = Source % 32; RegShift = Source % 32;
// Write set-enable register // Write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER + (4*RegOffset), 1 << RegShift); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -201,7 +200,7 @@ GetInterruptSourceState (
RegOffset = Source / 32; RegOffset = Source / 32;
RegShift = Source % 32; RegShift = Source % 32;
if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) { if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
*InterruptState = FALSE; *InterruptState = FALSE;
} else { } else {
*InterruptState = TRUE; *InterruptState = TRUE;
@ -233,7 +232,7 @@ EndOfInterrupt (
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, Source); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -258,9 +257,10 @@ IrqInterruptHandler (
UINT32 GicInterrupt; UINT32 GicInterrupt;
HARDWARE_INTERRUPT_HANDLER InterruptHandler; HARDWARE_INTERRUPT_HANDLER InterruptHandler;
GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCIAR); GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);
//TODO: Comment me
if (GicInterrupt >= PcdGet32(PcdGicNumInterrupts)) { if (GicInterrupt >= PcdGet32(PcdGicNumInterrupts)) {
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, GicInterrupt); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, GicInterrupt);
return; return;
} }
@ -323,11 +323,11 @@ ExitBootServicesEvent (
} }
// Disable Gic Interface // Disable Gic Interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x0); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0x0); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);
// Disable Gic Distributor // Disable Gic Distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x0); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);
} }
/** /**
@ -363,28 +363,28 @@ InterruptDxeInitialize (
RegOffset = Index / 4; RegOffset = Index / 4;
RegShift = (Index % 4) * 8; RegShift = (Index % 4) * 8;
MmioAndThenOr32 ( MmioAndThenOr32 (
PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR + (4*RegOffset), PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
~(0xff << RegShift), ~(0xff << RegShift),
GIC_DEFAULT_PRIORITY << RegShift ARM_GIC_DEFAULT_PRIORITY << RegShift
); );
} }
// Configure interrupts for cpu 0 // Configure interrupts for cpu 0
for (Index = 0; Index < GIC_NUM_REG_PER_INT_BYTES; Index++) { for (Index = 0; Index < ARM_GIC_NUM_REG_PER_INT_BYTES; Index++) {
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (Index*4), 0x01010101); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), 0x01010101);
} }
// Set binary point reg to 0x7 (no preemption) // Set binary point reg to 0x7 (no preemption)
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
// Set priority mask reg to 0xff to allow all priorities through // Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
// Enable gic cpu interface // Enable gic cpu interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1); MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
// Enable gic distributor // Enable gic distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1); MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers)); ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));

4
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
View File

@ -24,7 +24,6 @@
[Sources.common] [Sources.common]
PL390GicDxe.c PL390GicDxe.c
[Packages] [Packages]
MdePkg/MdePkg.dec MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec EmbeddedPkg/EmbeddedPkg.dec
@ -39,9 +38,6 @@
UefiDriverEntryPoint UefiDriverEntryPoint
IoLib IoLib
[Guids]
[Protocols] [Protocols]
gHardwareInterruptProtocolGuid gHardwareInterruptProtocolGuid
gEfiCpuArchProtocolGuid gEfiCpuArchProtocolGuid

7
ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf → ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
View File

@ -13,17 +13,16 @@
[Defines] [Defines]
INF_VERSION = 0x00010005 INF_VERSION = 0x00010005
BASE_NAME = PL390GicNonSec BASE_NAME = PL390GicLib
FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405 FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405
MODULE_TYPE = SEC MODULE_TYPE = SEC
VERSION_STRING = 1.0 VERSION_STRING = 1.0
LIBRARY_CLASS = PL390GicNonSecLib LIBRARY_CLASS = ArmGicLib
[Sources] [Sources]
PL390Gic.c
PL390GicNonSec.c PL390GicNonSec.c
[Packages] [Packages]
ArmPkg/ArmPkg.dec ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec MdePkg/MdePkg.dec
[FixedPcd]

64
ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
View File

@ -14,12 +14,12 @@
#include <Uefi.h> #include <Uefi.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Drivers/PL390Gic.h> #include <Library/ArmGicLib.h>
VOID VOID
EFIAPI EFIAPI
PL390GicEnableInterruptInterface ( ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
@ -27,12 +27,12 @@ PL390GicEnableInterruptInterface (
* Enable the CPU interface in Non-Secure world * Enable the CPU interface in Non-Secure world
* Note: The ICCICR register is banked when Security extensions are implemented * Note: The ICCICR register is banked when Security extensions are implemented
*/ */
MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001); MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,0x00000001);
} }
VOID VOID
EFIAPI EFIAPI
PL390GicEnableDistributor ( ArmGicEnableDistributor (
IN INTN GicDistributorBase IN INTN GicDistributorBase
) )
{ {
@ -40,59 +40,5 @@ PL390GicEnableDistributor (
* Enable GIC distributor in Non-Secure world. * Enable GIC distributor in Non-Secure world.
* Note: The ICDDCR register is banked when Security extensions are implemented * Note: The ICDDCR register is banked when Security extensions are implemented
*/ */
MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001); MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x00000001);
}
VOID
EFIAPI
PL390GicSendSgiTo (
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList
)
{
MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
}
UINT32
EFIAPI
PL390GicAcknowledgeSgiFrom (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId
)
{
INTN InterruptId;
InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
}
}
UINT32
EFIAPI
PL390GicAcknowledgeSgi2From (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId,
IN INTN SgiId
)
{
INTN InterruptId;
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
}
} }

95
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@ -14,7 +14,7 @@
#include <Uefi.h> #include <Uefi.h>
#include <Library/IoLib.h> #include <Library/IoLib.h>
#include <Drivers/PL390Gic.h> #include <Library/ArmGicLib.h>
/* /*
* This function configures the all interrupts to be Non-secure. * This function configures the all interrupts to be Non-secure.
@ -22,114 +22,59 @@
*/ */
VOID VOID
EFIAPI EFIAPI
PL390GicSetupNonSecure ( ArmGicSetupNonSecure (
IN INTN GicDistributorBase, IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR); UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
// Set priority Mask so that no interrupts get through to CPU // Set priority Mask so that no interrupts get through to CPU
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0); MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
// Check if there are any pending interrupts // Check if there are any pending interrupts
while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) { //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR); UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
// Write to End of interrupt signal // Write to End of interrupt signal
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId); MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
} }
// Ensure all GIC interrupts are Non-Secure // Ensure all GIC interrupts are Non-Secure
MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0] MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2) MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
// Ensure all interrupts can get through the priority mask // Ensure all interrupts can get through the priority mask
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask); MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
} }
VOID VOID
EFIAPI EFIAPI
PL390GicEnableInterruptInterface ( ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
/* /*
* Enable CPU interface in Secure world * Enable CPU interface in Secure world
* Enable CPU inteface in Non-secure World * Enable CPU inteface in Non-secure World
* Signal Secure Interrupts to CPU using FIQ line * * Signal Secure Interrupts to CPU using FIQ line *
*/ */
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR, MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,
GIC_ICCICR_ENABLE_SECURE(1) | ARM_GIC_ICCICR_ENABLE_SECURE |
GIC_ICCICR_ENABLE_NS(1) | ARM_GIC_ICCICR_ENABLE_NS |
GIC_ICCICR_ACK_CTL(0) | ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
GIC_ICCICR_USE_SBPR(0));
} }
VOID VOID
EFIAPI EFIAPI
PL390GicEnableDistributor ( ArmGicEnableDistributor (
IN INTN GicDistributorBase IN INTN GicDistributorBase
) )
{ {
MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1); // turn on the GIC distributor
}
VOID
EFIAPI
PL390GicSendSgiTo (
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList
)
{
MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
}
UINT32
EFIAPI
PL390GicAcknowledgeSgiFrom (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId
)
{
INTN InterruptId;
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
}
}
UINT32
EFIAPI
PL390GicAcknowledgeSgi2From (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId,
IN INTN SgiId
)
{
INTN InterruptId;
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
return 1;
} else {
return 0;
}
} }

7
ArmPkg/Drivers/PL390Gic/PL390GicSec.inf → ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
View File

@ -13,17 +13,16 @@
[Defines] [Defines]
INF_VERSION = 0x00010005 INF_VERSION = 0x00010005
BASE_NAME = PL390GicSec BASE_NAME = PL390GicSecLib
FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b
MODULE_TYPE = SEC MODULE_TYPE = SEC
VERSION_STRING = 1.0 VERSION_STRING = 1.0
LIBRARY_CLASS = PL390GicSecLib LIBRARY_CLASS = ArmGicSecLib
[Sources] [Sources]
PL390Gic.c
PL390GicSec.c PL390GicSec.c
[Packages] [Packages]
ArmPkg/ArmPkg.dec ArmPkg/ArmPkg.dec
MdePkg/MdePkg.dec MdePkg/MdePkg.dec
[FixedPcd]

120
ArmPkg/Include/Drivers/PL390Gic.h
View File

@ -1,120 +0,0 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __PL390GIC_H
#define __PL390GIC_H
//
// GIC definitions
//
// Distributor
#define GIC_ICDDCR 0x000 // Distributor Control Register
#define GIC_ICDICTR 0x004 // Interrupt Controller Type Register
#define GIC_ICDIIDR 0x008 // Implementer Identification Register
// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BITS (see GIC spec)
#define GIC_ICDISR 0x080 // Interrupt Security Registers
#define GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
#define GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
#define GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
#define GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
#define GIC_ICDABR 0x300 // Active Bit Registers
// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BYTES
#define GIC_ICDIPR 0x400 // Interrupt Priority Registers
// each reg base below repeats for VE_NUM_GIC_INTERRUPTS
#define GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
#define GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
// just one of these
#define GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
// Cpu interface
#define GIC_ICCICR 0x00 // CPU Interface Control Register
#define GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
#define GIC_ICCBPR 0x08 // Binary Point Register
#define GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
#define GIC_ICCEIOR 0x10 // End Of Interrupt Register
#define GIC_ICCRPR 0x14 // Running Priority Register
#define GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
#define GIC_ICCABPR 0x1C // Aliased Binary Point Register
#define GIC_ICCIDR 0xFC // Identification Register
#define GIC_ICDSGIR_FILTER_TARGETLIST 0x0
#define GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
#define GIC_ICDSGIR_FILTER_ITSELF 0x2
//Bit-masks to configure the CPU Interface Control register
#define GIC_ICCICR_ENABLE_SECURE(a) ((a << 0) & 0x01)
#define GIC_ICCICR_ENABLE_NS(a) ((a << 1) & 0x02)
#define GIC_ICCICR_ACK_CTL(a) ((a << 2) & 0x04)
#define GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(a)((a << 3) & 0x08)
#define GIC_ICCICR_USE_SBPR(a) ((a << 4) & 0x10)
//
// GIC SEC interfaces
//
VOID
EFIAPI
PL390GicSetupNonSecure (
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
PL390GicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
PL390GicEnableDistributor (
IN INTN GicDistributorBase
);
VOID
EFIAPI
PL390GicSendSgiTo (
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList
);
UINT32
EFIAPI
PL390GicAcknowledgeSgiFrom (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId
);
UINT32
EFIAPI
PL390GicAcknowledgeSgi2From (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId,
IN INTN SgiId
);
UINTN
EFIAPI
PL390GicSetPriorityMask (
IN INTN GicInterruptInterfaceBase,
IN INTN PriorityMask
);
#endif

126
ArmPkg/Include/Library/ArmGicLib.h Normal file
View File

@ -0,0 +1,126 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __PL390GIC_H
#define __PL390GIC_H
//
// GIC definitions
//
//
// GIC Distributor
//
#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)
#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES
#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS
#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
// just one of these
#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
//
// GIC Cpu interface
//
#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
#define ARM_GIC_ICCIDR 0xFC // Identification Register
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
// Bit-masks to configure the CPU Interface Control register
#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
#define ARM_GIC_ICCICR_ENABLE_NS 0x02
#define ARM_GIC_ICCICR_ACK_CTL 0x04
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
#define ARM_GIC_ICCICR_USE_SBPR 0x10
//
// GIC SEC interfaces
//
VOID
EFIAPI
ArmGicSetupNonSecure (
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicEnableDistributor (
IN INTN GicDistributorBase
);
VOID
EFIAPI
ArmGicSendSgiTo (
IN INTN GicDistributorBase,
IN INTN TargetListFilter,
IN INTN CPUTargetList
);
UINT32
EFIAPI
ArmGicAcknowledgeSgiFrom (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId
);
UINT32
EFIAPI
ArmGicAcknowledgeSgi2From (
IN INTN GicInterruptInterfaceBase,
IN INTN CoreId,
IN INTN SgiId
);
UINTN
EFIAPI
ArmGicSetPriorityMask (
IN INTN GicInterruptInterfaceBase,
IN INTN PriorityMask
);
#endif

5
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A8.dsc
View File

@ -136,7 +136,7 @@
# L2 Cache Driver # L2 Cache Driver
L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure # ARM PL390 General Interrupt Driver in Secure and Non-secure
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
@ -441,13 +441,14 @@
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
ArmPlatformPkg/PrePi/PeiUniCore.inf { ArmPlatformPkg/PrePi/PeiUniCore.inf {
<LibraryClasses> <LibraryClasses>
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
} }
!else !else
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf { ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf {
<LibraryClasses> <LibraryClasses>
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
} }
MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf { MdeModulePkg/Universal/PCD/Pei/Pcd.inf {

8
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb-RTSM-A9x2.dsc
View File

@ -115,7 +115,8 @@
# ARM PL011 UART Driver # ARM PL011 UART Driver
PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure # ARM PL390 General Interrupt Driver in Secure and Non-secure
PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
@ -138,8 +139,6 @@
# L2 Cache Driver # L2 Cache Driver
L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
# ARM PL390 General Interrupt Driver in Secure
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
@ -451,13 +450,14 @@
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
ArmPlatformPkg/PrePi/PeiMPCore.inf { ArmPlatformPkg/PrePi/PeiMPCore.inf {
<LibraryClasses> <LibraryClasses>
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
} }
!else !else
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf { ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
<LibraryClasses> <LibraryClasses>
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
} }
MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf { MdeModulePkg/Universal/PCD/Pei/Pcd.inf {

7
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc
View File

@ -147,8 +147,8 @@
#DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure # ARM PL390 General Interrupt Driver in Secure and Non-secure
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
@ -496,13 +496,14 @@
!if $(EDK2_SKIP_PEICORE) == 1 !if $(EDK2_SKIP_PEICORE) == 1
ArmPlatformPkg/PrePi/PeiMPCore.inf { ArmPlatformPkg/PrePi/PeiMPCore.inf {
<LibraryClasses> <LibraryClasses>
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
} }
!else !else
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf { ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
<LibraryClasses> <LibraryClasses>
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
} }
MdeModulePkg/Core/Pei/PeiMain.inf MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf { MdeModulePkg/Universal/PCD/Pei/Pcd.inf {

6
ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.c
View File

@ -14,12 +14,12 @@
#include <PiPei.h> #include <PiPei.h>
#include <Library/ArmGicLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/PrintLib.h> #include <Library/PrintLib.h>
#include <Library/SerialPortLib.h> #include <Library/SerialPortLib.h>
#include <Chipset/ArmV7.h> #include <Chipset/ArmV7.h>
#include <Drivers/PL390Gic.h>
#define ARM_PRIMARY_CORE 0 #define ARM_PRIMARY_CORE 0
@ -38,7 +38,7 @@ NonSecureWaitForFirmware (
ArmCallWFI(); ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal. // Acknowledge the interrupt and send End of Interrupt signal.
PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE); ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
// Jump to secondary core entry point. // Jump to secondary core entry point.
secondary_start (); secondary_start ();
@ -87,7 +87,7 @@ ArmPlatformSecExtraAction (
} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) { } else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
if (CoreId == ARM_PRIMARY_CORE) { if (CoreId == ARM_PRIMARY_CORE) {
// Signal the secondary cores they can jump to PEI phase // Signal the secondary cores they can jump to PEI phase
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
// To enter into Non Secure state, we need to make a return from exception // To enter into Non Secure state, we need to make a return from exception
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress); *JumpAddress = PcdGet32(PcdNormalFvBaseAddress);

2
ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
View File

@ -36,7 +36,7 @@
[LibraryClasses] [LibraryClasses]
DebugLib DebugLib
PcdLib PcdLib
PL390GicSecLib ArmGicSecLib
PrintLib PrintLib
SerialPortLib SerialPortLib

12
ArmPlatformPkg/PrePeiCore/MainMPCore.c
View File

@ -12,9 +12,9 @@
* *
**/ **/
#include <Library/ArmGicLib.h>
#include <Library/ArmMPCoreMailBoxLib.h> #include <Library/ArmMPCoreMailBoxLib.h>
#include <Chipset/ArmV7.h> #include <Chipset/ArmV7.h>
#include <Drivers/PL390Gic.h>
#include "PrePeiCore.h" #include "PrePeiCore.h"
@ -45,7 +45,7 @@ SecondaryMain (
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) { while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
ArmCallWFI(); ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal. // Acknowledge the interrupt and send End of Interrupt signal.
PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/); ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
} }
secondary_start = (VOID (*)())secondary_entry_addr; secondary_start = (VOID (*)())secondary_entry_addr;
@ -65,13 +65,13 @@ PrimaryMain (
{ {
EFI_SEC_PEI_HAND_OFF SecCoreData; EFI_SEC_PEI_HAND_OFF SecCoreData;
//Enable the GIC Distributor // Enable the GIC Distributor
PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase)); ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores // If ArmVe has not been built as Standalone then we need to wake up the secondary cores
if (FeaturePcdGet(PcdSendSgiToBringUpSecondaryCores)) { if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces // Sending SGI to all the Secondary CPU interfaces
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
} }
// //

2
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
View File

@ -44,7 +44,7 @@
DebugLib DebugLib
DebugAgentLib DebugAgentLib
IoLib IoLib
PL390GicNonSecLib ArmGicLib
PrintLib PrintLib
SerialPortLib SerialPortLib

10
ArmPlatformPkg/PrePi/MainMPCore.c
View File

@ -14,9 +14,9 @@
#include "PrePi.h" #include "PrePi.h"
#include <Library/ArmGicLib.h>
#include <Library/ArmMPCoreMailBoxLib.h> #include <Library/ArmMPCoreMailBoxLib.h>
#include <Chipset/ArmV7.h> #include <Chipset/ArmV7.h>
#include <Drivers/PL390Gic.h>
VOID VOID
PrimaryMain ( PrimaryMain (
@ -24,13 +24,13 @@ PrimaryMain (
IN UINT64 StartTimeStamp IN UINT64 StartTimeStamp
) )
{ {
//Enable the GIC Distributor // Enable the GIC Distributor
PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase)); ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization
if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) { if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {
// Sending SGI to all the Secondary CPU interfaces // Sending SGI to all the Secondary CPU interfaces
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
} }
PrePiMain (UefiMemoryBase, StartTimeStamp); PrePiMain (UefiMemoryBase, StartTimeStamp);
@ -54,7 +54,7 @@ SecondaryMain (
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) { while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
ArmCallWFI(); ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal. // Acknowledge the interrupt and send End of Interrupt signal.
PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/); ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
} }
secondary_start = (VOID (*)())secondary_entry_addr; secondary_start = (VOID (*)())secondary_entry_addr;

2
ArmPlatformPkg/PrePi/PeiMPCore.inf
View File

@ -40,7 +40,7 @@
DebugAgentLib DebugAgentLib
ArmLib ArmLib
ArmMPCoreMailBoxLib ArmMPCoreMailBoxLib
PL390GicNonSecLib ArmGicLib
IoLib IoLib
TimerLib TimerLib
SerialPortLib SerialPortLib

18
ArmPlatformPkg/Sec/Sec.c
View File

@ -24,7 +24,7 @@
#include <Library/ArmPlatformLib.h> #include <Library/ArmPlatformLib.h>
#include <Chipset/ArmV7.h> #include <Chipset/ArmV7.h>
#include <Drivers/PL390Gic.h> #include <Library/ArmGicLib.h>
#define ARM_PRIMARY_CORE 0 #define ARM_PRIMARY_CORE 0
@ -160,27 +160,27 @@ CEntryPoint (
// 3: As all the cores are in secure state, use secure SGI's // 3: As all the cores are in secure state, use secure SGI's
// //
PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase)); ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Send SGI to all Secondary core to wake them up from WFI state. // Send SGI to all Secondary core to wake them up from WFI state.
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E); ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
} else { } else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done // The secondary cores need to wait until the Trustzone chipsets configuration is done
// before switching to Non Secure World // before switching to Non Secure World
// Enabled GIC CPU Interface // Enabled GIC CPU Interface
PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Waiting for the SGI from the primary core // Waiting for the SGI from the primary core
ArmCallWFI(); ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal. // Acknowledge the interrupt and send End of Interrupt signal.
PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE); ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
} }
// Transfer the interrupt to Non-secure World // Transfer the interrupt to Non-secure World
PL390GicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase)); ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register : // Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World // - Enable CP10 and CP11 accesses in NS World
@ -199,9 +199,9 @@ CEntryPoint (
// Trustzone is not enabled, just enable the Distributor and CPU interface // Trustzone is not enabled, just enable the Distributor and CPU interface
if (CoreId == ARM_PRIMARY_CORE) { if (CoreId == ARM_PRIMARY_CORE) {
PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase)); ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
} }
PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase)); ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception(). // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program

2
ArmPlatformPkg/Sec/Sec.inf
View File

@ -42,7 +42,7 @@
DebugLib DebugLib
DebugAgentLib DebugAgentLib
IoLib IoLib
PL390GicSecLib ArmGicSecLib
PrintLib PrintLib
SerialPortLib SerialPortLib