mirror of https://github.com/acidanthera/audk.git
ArmPkg: Renamed library 'PL390GicLib' into 'ArmGicLib'
This library is the interface for the ARM Generic Interrupt Controller Architecture Specification. ARM Platform can use any GIC controller (not necessary PL390 GIC). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12411 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
75e4db2d3b
commit
55a0d64b88
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@ -120,6 +120,7 @@
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ArmPkg/Drivers/CpuDxe/CpuDxe.inf
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ArmPkg/Drivers/CpuPei/CpuPei.inf
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ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
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ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
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ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
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ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
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ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
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ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
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@ -0,0 +1,71 @@
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/** @file
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#include <Library/ArmGicLib.h>
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VOID
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EFIAPI
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ArmGicSendSgiTo (
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IN INTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList
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)
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{
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
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}
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UINT32
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EFIAPI
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ArmGicAcknowledgeSgiFrom (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId
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)
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{
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INTN InterruptId;
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InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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}
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UINT32
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EFIAPI
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ArmGicAcknowledgeSgi2From (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId,
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IN INTN SgiId
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)
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{
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INTN InterruptId;
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InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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}
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@ -29,25 +29,24 @@ Abstract:
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#include <Library/UefiLib.h>
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/ArmGicLib.h>
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#include <Protocol/Cpu.h>
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#include <Protocol/HardwareInterrupt.h>
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#include <Drivers/PL390Gic.h>
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// number of 32-bit registers needed to represent those interrupts as a bit
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// (used for enable set, enable clear, pending set, pending clear, and active regs)
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#define GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32)
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#define ARM_GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32)
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// number of 32-bit registers needed to represent those interrupts as two bits
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// (used for configuration reg)
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#define GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16)
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#define ARM_GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16)
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// number of 32-bit registers needed to represent interrupts as 8-bit priority field
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// (used for priority regs)
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#define GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4)
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#define ARM_GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4)
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#define GIC_DEFAULT_PRIORITY 0x80
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#define ARM_GIC_DEFAULT_PRIORITY 0x80
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extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
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@ -130,7 +129,7 @@ EnableInterruptSource (
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RegShift = Source % 32;
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// write set-enable register
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset), 1 << RegShift);
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
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return EFI_SUCCESS;
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}
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@ -165,7 +164,7 @@ DisableInterruptSource (
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RegShift = Source % 32;
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// Write set-enable register
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER + (4*RegOffset), 1 << RegShift);
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
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return EFI_SUCCESS;
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}
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@ -201,7 +200,7 @@ GetInterruptSourceState (
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RegOffset = Source / 32;
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RegShift = Source % 32;
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if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
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if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
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*InterruptState = FALSE;
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} else {
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*InterruptState = TRUE;
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@ -233,7 +232,7 @@ EndOfInterrupt (
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return EFI_UNSUPPORTED;
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}
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, Source);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);
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return EFI_SUCCESS;
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}
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@ -258,9 +257,10 @@ IrqInterruptHandler (
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UINT32 GicInterrupt;
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HARDWARE_INTERRUPT_HANDLER InterruptHandler;
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GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCIAR);
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GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);
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//TODO: Comment me
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if (GicInterrupt >= PcdGet32(PcdGicNumInterrupts)) {
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, GicInterrupt);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, GicInterrupt);
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return;
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}
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@ -323,11 +323,11 @@ ExitBootServicesEvent (
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}
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// Disable Gic Interface
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x0);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0x0);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);
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// Disable Gic Distributor
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x0);
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);
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}
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/**
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@ -363,28 +363,28 @@ InterruptDxeInitialize (
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RegOffset = Index / 4;
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RegShift = (Index % 4) * 8;
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MmioAndThenOr32 (
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PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR + (4*RegOffset),
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PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
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~(0xff << RegShift),
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GIC_DEFAULT_PRIORITY << RegShift
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ARM_GIC_DEFAULT_PRIORITY << RegShift
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);
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}
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// Configure interrupts for cpu 0
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for (Index = 0; Index < GIC_NUM_REG_PER_INT_BYTES; Index++) {
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (Index*4), 0x01010101);
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for (Index = 0; Index < ARM_GIC_NUM_REG_PER_INT_BYTES; Index++) {
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), 0x01010101);
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}
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// Set binary point reg to 0x7 (no preemption)
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
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// Set priority mask reg to 0xff to allow all priorities through
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
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// Enable gic cpu interface
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1);
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MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
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// Enable gic distributor
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1);
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MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
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ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));
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@ -24,7 +24,6 @@
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[Sources.common]
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PL390GicDxe.c
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[Packages]
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MdePkg/MdePkg.dec
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EmbeddedPkg/EmbeddedPkg.dec
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@ -39,9 +38,6 @@
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UefiDriverEntryPoint
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IoLib
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[Guids]
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[Protocols]
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gHardwareInterruptProtocolGuid
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gEfiCpuArchProtocolGuid
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@ -13,17 +13,16 @@
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = PL390GicNonSec
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BASE_NAME = PL390GicLib
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FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405
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MODULE_TYPE = SEC
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VERSION_STRING = 1.0
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LIBRARY_CLASS = PL390GicNonSecLib
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LIBRARY_CLASS = ArmGicLib
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[Sources]
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PL390Gic.c
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PL390GicNonSec.c
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[Packages]
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ArmPkg/ArmPkg.dec
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MdePkg/MdePkg.dec
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[FixedPcd]
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@ -14,12 +14,12 @@
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#include <Drivers/PL390Gic.h>
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#include <Library/ArmGicLib.h>
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VOID
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EFIAPI
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PL390GicEnableInterruptInterface (
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ArmGicEnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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@ -27,12 +27,12 @@ PL390GicEnableInterruptInterface (
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* Enable the CPU interface in Non-Secure world
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* Note: The ICCICR register is banked when Security extensions are implemented
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*/
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MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,0x00000001);
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}
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VOID
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EFIAPI
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PL390GicEnableDistributor (
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ArmGicEnableDistributor (
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IN INTN GicDistributorBase
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)
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{
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@ -40,59 +40,5 @@ PL390GicEnableDistributor (
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* Enable GIC distributor in Non-Secure world.
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* Note: The ICDDCR register is banked when Security extensions are implemented
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*/
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MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001);
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}
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VOID
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EFIAPI
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PL390GicSendSgiTo (
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IN INTN GicDistributorBase,
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IN INTN TargetListFilter,
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IN INTN CPUTargetList
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)
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{
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MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
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}
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UINT32
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EFIAPI
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PL390GicAcknowledgeSgiFrom (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId
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)
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{
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INTN InterruptId;
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InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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}
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UINT32
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EFIAPI
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PL390GicAcknowledgeSgi2From (
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IN INTN GicInterruptInterfaceBase,
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IN INTN CoreId,
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IN INTN SgiId
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)
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{
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INTN InterruptId;
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InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
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if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
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// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
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MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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return 1;
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} else {
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return 0;
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}
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x00000001);
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}
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@ -14,7 +14,7 @@
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#include <Uefi.h>
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#include <Library/IoLib.h>
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#include <Drivers/PL390Gic.h>
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#include <Library/ArmGicLib.h>
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/*
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* This function configures the all interrupts to be Non-secure.
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@ -22,114 +22,59 @@
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*/
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VOID
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EFIAPI
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PL390GicSetupNonSecure (
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ArmGicSetupNonSecure (
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IN INTN GicDistributorBase,
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);
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UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
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// Set priority Mask so that no interrupts get through to CPU
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
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// Check if there are any pending interrupts
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while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {
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//TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
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while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
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// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
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UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
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UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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// Write to End of interrupt signal
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
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}
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// Ensure all GIC interrupts are Non-Secure
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MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
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MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
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MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
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// Ensure all interrupts can get through the priority mask
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MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
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}
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VOID
|
||||
EFIAPI
|
||||
PL390GicEnableInterruptInterface (
|
||||
ArmGicEnableInterruptInterface (
|
||||
IN INTN GicInterruptInterfaceBase
|
||||
)
|
||||
{
|
||||
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
|
||||
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
|
||||
|
||||
/*
|
||||
* Enable CPU interface in Secure world
|
||||
* Enable CPU inteface in Non-secure World
|
||||
* Signal Secure Interrupts to CPU using FIQ line *
|
||||
*/
|
||||
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,
|
||||
GIC_ICCICR_ENABLE_SECURE(1) |
|
||||
GIC_ICCICR_ENABLE_NS(1) |
|
||||
GIC_ICCICR_ACK_CTL(0) |
|
||||
GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |
|
||||
GIC_ICCICR_USE_SBPR(0));
|
||||
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,
|
||||
ARM_GIC_ICCICR_ENABLE_SECURE |
|
||||
ARM_GIC_ICCICR_ENABLE_NS |
|
||||
ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicEnableDistributor (
|
||||
ArmGicEnableDistributor (
|
||||
IN INTN GicDistributorBase
|
||||
)
|
||||
{
|
||||
MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor
|
||||
}
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicSendSgiTo (
|
||||
IN INTN GicDistributorBase,
|
||||
IN INTN TargetListFilter,
|
||||
IN INTN CPUTargetList
|
||||
)
|
||||
{
|
||||
MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
|
||||
}
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
PL390GicAcknowledgeSgiFrom (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN CoreId
|
||||
)
|
||||
{
|
||||
INTN InterruptId;
|
||||
|
||||
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
|
||||
|
||||
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
|
||||
if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
|
||||
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
|
||||
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
PL390GicAcknowledgeSgi2From (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN CoreId,
|
||||
IN INTN SgiId
|
||||
)
|
||||
{
|
||||
INTN InterruptId;
|
||||
|
||||
InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
|
||||
|
||||
// Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
|
||||
if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
|
||||
// Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
|
||||
MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1); // turn on the GIC distributor
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,17 +13,16 @@
|
|||
|
||||
[Defines]
|
||||
INF_VERSION = 0x00010005
|
||||
BASE_NAME = PL390GicSec
|
||||
BASE_NAME = PL390GicSecLib
|
||||
FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b
|
||||
MODULE_TYPE = SEC
|
||||
VERSION_STRING = 1.0
|
||||
LIBRARY_CLASS = PL390GicSecLib
|
||||
LIBRARY_CLASS = ArmGicSecLib
|
||||
|
||||
[Sources]
|
||||
PL390Gic.c
|
||||
PL390GicSec.c
|
||||
|
||||
[Packages]
|
||||
ArmPkg/ArmPkg.dec
|
||||
MdePkg/MdePkg.dec
|
||||
|
||||
[FixedPcd]
|
||||
|
|
@ -1,120 +0,0 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __PL390GIC_H
|
||||
#define __PL390GIC_H
|
||||
|
||||
//
|
||||
// GIC definitions
|
||||
//
|
||||
|
||||
// Distributor
|
||||
#define GIC_ICDDCR 0x000 // Distributor Control Register
|
||||
#define GIC_ICDICTR 0x004 // Interrupt Controller Type Register
|
||||
#define GIC_ICDIIDR 0x008 // Implementer Identification Register
|
||||
|
||||
// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BITS (see GIC spec)
|
||||
#define GIC_ICDISR 0x080 // Interrupt Security Registers
|
||||
#define GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
|
||||
#define GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
|
||||
#define GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
|
||||
#define GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
|
||||
#define GIC_ICDABR 0x300 // Active Bit Registers
|
||||
|
||||
// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BYTES
|
||||
#define GIC_ICDIPR 0x400 // Interrupt Priority Registers
|
||||
|
||||
// each reg base below repeats for VE_NUM_GIC_INTERRUPTS
|
||||
#define GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
|
||||
#define GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
|
||||
|
||||
// just one of these
|
||||
#define GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
|
||||
|
||||
// Cpu interface
|
||||
#define GIC_ICCICR 0x00 // CPU Interface Control Register
|
||||
#define GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
|
||||
#define GIC_ICCBPR 0x08 // Binary Point Register
|
||||
#define GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
|
||||
#define GIC_ICCEIOR 0x10 // End Of Interrupt Register
|
||||
#define GIC_ICCRPR 0x14 // Running Priority Register
|
||||
#define GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
|
||||
#define GIC_ICCABPR 0x1C // Aliased Binary Point Register
|
||||
#define GIC_ICCIDR 0xFC // Identification Register
|
||||
|
||||
#define GIC_ICDSGIR_FILTER_TARGETLIST 0x0
|
||||
#define GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
|
||||
#define GIC_ICDSGIR_FILTER_ITSELF 0x2
|
||||
|
||||
//Bit-masks to configure the CPU Interface Control register
|
||||
#define GIC_ICCICR_ENABLE_SECURE(a) ((a << 0) & 0x01)
|
||||
#define GIC_ICCICR_ENABLE_NS(a) ((a << 1) & 0x02)
|
||||
#define GIC_ICCICR_ACK_CTL(a) ((a << 2) & 0x04)
|
||||
#define GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(a)((a << 3) & 0x08)
|
||||
#define GIC_ICCICR_USE_SBPR(a) ((a << 4) & 0x10)
|
||||
|
||||
|
||||
//
|
||||
// GIC SEC interfaces
|
||||
//
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicSetupNonSecure (
|
||||
IN INTN GicDistributorBase,
|
||||
IN INTN GicInterruptInterfaceBase
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicEnableInterruptInterface (
|
||||
IN INTN GicInterruptInterfaceBase
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicEnableDistributor (
|
||||
IN INTN GicDistributorBase
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
PL390GicSendSgiTo (
|
||||
IN INTN GicDistributorBase,
|
||||
IN INTN TargetListFilter,
|
||||
IN INTN CPUTargetList
|
||||
);
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
PL390GicAcknowledgeSgiFrom (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN CoreId
|
||||
);
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
PL390GicAcknowledgeSgi2From (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN CoreId,
|
||||
IN INTN SgiId
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
PL390GicSetPriorityMask (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN PriorityMask
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
/** @file
|
||||
*
|
||||
* Copyright (c) 2011, ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program and the accompanying materials
|
||||
* are licensed and made available under the terms and conditions of the BSD License
|
||||
* which accompanies this distribution. The full text of the license may be found at
|
||||
* http://opensource.org/licenses/bsd-license.php
|
||||
*
|
||||
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
*
|
||||
**/
|
||||
|
||||
#ifndef __PL390GIC_H
|
||||
#define __PL390GIC_H
|
||||
|
||||
//
|
||||
// GIC definitions
|
||||
//
|
||||
|
||||
//
|
||||
// GIC Distributor
|
||||
//
|
||||
#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
|
||||
#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
|
||||
#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
|
||||
|
||||
// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)
|
||||
#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
|
||||
#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
|
||||
#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
|
||||
#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
|
||||
#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
|
||||
#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
|
||||
|
||||
// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES
|
||||
#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
|
||||
|
||||
// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS
|
||||
#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
|
||||
#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
|
||||
|
||||
#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
|
||||
|
||||
// just one of these
|
||||
#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
|
||||
|
||||
//
|
||||
// GIC Cpu interface
|
||||
//
|
||||
#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
|
||||
#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
|
||||
#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
|
||||
#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
|
||||
#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
|
||||
#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
|
||||
#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
|
||||
#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
|
||||
#define ARM_GIC_ICCIDR 0xFC // Identification Register
|
||||
|
||||
#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
|
||||
#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
|
||||
#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
|
||||
|
||||
// Bit-masks to configure the CPU Interface Control register
|
||||
#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
|
||||
#define ARM_GIC_ICCICR_ENABLE_NS 0x02
|
||||
#define ARM_GIC_ICCICR_ACK_CTL 0x04
|
||||
#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
|
||||
#define ARM_GIC_ICCICR_USE_SBPR 0x10
|
||||
|
||||
|
||||
//
|
||||
// GIC SEC interfaces
|
||||
//
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmGicSetupNonSecure (
|
||||
IN INTN GicDistributorBase,
|
||||
IN INTN GicInterruptInterfaceBase
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmGicEnableInterruptInterface (
|
||||
IN INTN GicInterruptInterfaceBase
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmGicEnableDistributor (
|
||||
IN INTN GicDistributorBase
|
||||
);
|
||||
|
||||
VOID
|
||||
EFIAPI
|
||||
ArmGicSendSgiTo (
|
||||
IN INTN GicDistributorBase,
|
||||
IN INTN TargetListFilter,
|
||||
IN INTN CPUTargetList
|
||||
);
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
ArmGicAcknowledgeSgiFrom (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN CoreId
|
||||
);
|
||||
|
||||
UINT32
|
||||
EFIAPI
|
||||
ArmGicAcknowledgeSgi2From (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN CoreId,
|
||||
IN INTN SgiId
|
||||
);
|
||||
|
||||
UINTN
|
||||
EFIAPI
|
||||
ArmGicSetPriorityMask (
|
||||
IN INTN GicInterruptInterfaceBase,
|
||||
IN INTN PriorityMask
|
||||
);
|
||||
|
||||
#endif
|
||||
|
|
@ -136,7 +136,7 @@
|
|||
# L2 Cache Driver
|
||||
L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
|
||||
# ARM PL390 General Interrupt Driver in Secure and Non-secure
|
||||
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
|
||||
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
|
||||
|
||||
!if $(EDK2_SKIP_PEICORE) == 1
|
||||
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
|
||||
|
|
@ -441,13 +441,14 @@
|
|||
!if $(EDK2_SKIP_PEICORE) == 1
|
||||
ArmPlatformPkg/PrePi/PeiUniCore.inf {
|
||||
<LibraryClasses>
|
||||
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
|
||||
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
|
||||
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
|
||||
}
|
||||
!else
|
||||
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf {
|
||||
<LibraryClasses>
|
||||
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
|
||||
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
|
||||
}
|
||||
MdeModulePkg/Core/Pei/PeiMain.inf
|
||||
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
|
||||
|
|
|
|||
|
|
@ -115,7 +115,8 @@
|
|||
# ARM PL011 UART Driver
|
||||
PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
|
||||
# ARM PL390 General Interrupt Driver in Secure and Non-secure
|
||||
PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
|
||||
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
|
||||
ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
|
||||
|
||||
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
|
||||
|
||||
|
|
@ -138,8 +139,6 @@
|
|||
|
||||
# L2 Cache Driver
|
||||
L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf
|
||||
# ARM PL390 General Interrupt Driver in Secure
|
||||
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
|
||||
|
||||
!if $(EDK2_SKIP_PEICORE) == 1
|
||||
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
|
||||
|
|
@ -451,13 +450,14 @@
|
|||
!if $(EDK2_SKIP_PEICORE) == 1
|
||||
ArmPlatformPkg/PrePi/PeiMPCore.inf {
|
||||
<LibraryClasses>
|
||||
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
|
||||
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
|
||||
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf
|
||||
}
|
||||
!else
|
||||
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
|
||||
<LibraryClasses>
|
||||
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
|
||||
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
|
||||
}
|
||||
MdeModulePkg/Core/Pei/PeiMain.inf
|
||||
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
|
||||
|
|
|
|||
|
|
@ -147,8 +147,8 @@
|
|||
#DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
|
||||
|
||||
# ARM PL390 General Interrupt Driver in Secure and Non-secure
|
||||
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
|
||||
PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
|
||||
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
|
||||
ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
|
||||
|
||||
!if $(EDK2_SKIP_PEICORE) == 1
|
||||
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
|
||||
|
|
@ -496,13 +496,14 @@
|
|||
!if $(EDK2_SKIP_PEICORE) == 1
|
||||
ArmPlatformPkg/PrePi/PeiMPCore.inf {
|
||||
<LibraryClasses>
|
||||
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
|
||||
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
|
||||
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
|
||||
}
|
||||
!else
|
||||
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
|
||||
<LibraryClasses>
|
||||
PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
|
||||
ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
|
||||
}
|
||||
MdeModulePkg/Core/Pei/PeiMain.inf
|
||||
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
|
||||
|
|
|
|||
|
|
@ -14,12 +14,12 @@
|
|||
|
||||
#include <PiPei.h>
|
||||
|
||||
#include <Library/ArmGicLib.h>
|
||||
#include <Library/DebugLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/PrintLib.h>
|
||||
#include <Library/SerialPortLib.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Drivers/PL390Gic.h>
|
||||
|
||||
#define ARM_PRIMARY_CORE 0
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ NonSecureWaitForFirmware (
|
|||
ArmCallWFI();
|
||||
|
||||
// Acknowledge the interrupt and send End of Interrupt signal.
|
||||
PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
|
||||
ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
|
||||
|
||||
// Jump to secondary core entry point.
|
||||
secondary_start ();
|
||||
|
|
@ -87,7 +87,7 @@ ArmPlatformSecExtraAction (
|
|||
} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {
|
||||
if (CoreId == ARM_PRIMARY_CORE) {
|
||||
// Signal the secondary cores they can jump to PEI phase
|
||||
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
|
||||
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
|
||||
|
||||
// To enter into Non Secure state, we need to make a return from exception
|
||||
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
[LibraryClasses]
|
||||
DebugLib
|
||||
PcdLib
|
||||
PL390GicSecLib
|
||||
ArmGicSecLib
|
||||
PrintLib
|
||||
SerialPortLib
|
||||
|
||||
|
|
|
|||
|
|
@ -12,9 +12,9 @@
|
|||
*
|
||||
**/
|
||||
|
||||
#include <Library/ArmGicLib.h>
|
||||
#include <Library/ArmMPCoreMailBoxLib.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Drivers/PL390Gic.h>
|
||||
|
||||
#include "PrePeiCore.h"
|
||||
|
||||
|
|
@ -45,7 +45,7 @@ SecondaryMain (
|
|||
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
|
||||
ArmCallWFI();
|
||||
// Acknowledge the interrupt and send End of Interrupt signal.
|
||||
PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
|
||||
ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
|
||||
}
|
||||
|
||||
secondary_start = (VOID (*)())secondary_entry_addr;
|
||||
|
|
@ -65,13 +65,13 @@ PrimaryMain (
|
|||
{
|
||||
EFI_SEC_PEI_HAND_OFF SecCoreData;
|
||||
|
||||
//Enable the GIC Distributor
|
||||
PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
|
||||
// Enable the GIC Distributor
|
||||
ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
|
||||
|
||||
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
|
||||
if (FeaturePcdGet(PcdSendSgiToBringUpSecondaryCores)) {
|
||||
if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
|
||||
// Sending SGI to all the Secondary CPU interfaces
|
||||
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
|
||||
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
|
||||
}
|
||||
|
||||
//
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
DebugLib
|
||||
DebugAgentLib
|
||||
IoLib
|
||||
PL390GicNonSecLib
|
||||
ArmGicLib
|
||||
PrintLib
|
||||
SerialPortLib
|
||||
|
||||
|
|
|
|||
|
|
@ -14,9 +14,9 @@
|
|||
|
||||
#include "PrePi.h"
|
||||
|
||||
#include <Library/ArmGicLib.h>
|
||||
#include <Library/ArmMPCoreMailBoxLib.h>
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Drivers/PL390Gic.h>
|
||||
|
||||
VOID
|
||||
PrimaryMain (
|
||||
|
|
@ -24,13 +24,13 @@ PrimaryMain (
|
|||
IN UINT64 StartTimeStamp
|
||||
)
|
||||
{
|
||||
//Enable the GIC Distributor
|
||||
PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));
|
||||
// Enable the GIC Distributor
|
||||
ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
|
||||
|
||||
// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization
|
||||
if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {
|
||||
// Sending SGI to all the Secondary CPU interfaces
|
||||
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
|
||||
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
|
||||
}
|
||||
|
||||
PrePiMain (UefiMemoryBase, StartTimeStamp);
|
||||
|
|
@ -54,7 +54,7 @@ SecondaryMain (
|
|||
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {
|
||||
ArmCallWFI();
|
||||
// Acknowledge the interrupt and send End of Interrupt signal.
|
||||
PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
|
||||
ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);
|
||||
}
|
||||
|
||||
secondary_start = (VOID (*)())secondary_entry_addr;
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
DebugAgentLib
|
||||
ArmLib
|
||||
ArmMPCoreMailBoxLib
|
||||
PL390GicNonSecLib
|
||||
ArmGicLib
|
||||
IoLib
|
||||
TimerLib
|
||||
SerialPortLib
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include <Library/ArmPlatformLib.h>
|
||||
|
||||
#include <Chipset/ArmV7.h>
|
||||
#include <Drivers/PL390Gic.h>
|
||||
#include <Library/ArmGicLib.h>
|
||||
|
||||
#define ARM_PRIMARY_CORE 0
|
||||
|
||||
|
|
@ -160,27 +160,27 @@ CEntryPoint (
|
|||
// 3: As all the cores are in secure state, use secure SGI's
|
||||
//
|
||||
|
||||
PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
|
||||
PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
|
||||
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
|
||||
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
|
||||
|
||||
// Send SGI to all Secondary core to wake them up from WFI state.
|
||||
PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
|
||||
ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
|
||||
} else {
|
||||
// The secondary cores need to wait until the Trustzone chipsets configuration is done
|
||||
// before switching to Non Secure World
|
||||
|
||||
// Enabled GIC CPU Interface
|
||||
PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
|
||||
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
|
||||
|
||||
// Waiting for the SGI from the primary core
|
||||
ArmCallWFI();
|
||||
|
||||
// Acknowledge the interrupt and send End of Interrupt signal.
|
||||
PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
|
||||
ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
|
||||
}
|
||||
|
||||
// Transfer the interrupt to Non-secure World
|
||||
PL390GicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
|
||||
ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
|
||||
|
||||
// Write to CP15 Non-secure Access Control Register :
|
||||
// - Enable CP10 and CP11 accesses in NS World
|
||||
|
|
@ -199,9 +199,9 @@ CEntryPoint (
|
|||
|
||||
// Trustzone is not enabled, just enable the Distributor and CPU interface
|
||||
if (CoreId == ARM_PRIMARY_CORE) {
|
||||
PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
|
||||
ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
|
||||
}
|
||||
PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
|
||||
ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
|
||||
|
||||
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
|
||||
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@
|
|||
DebugLib
|
||||
DebugAgentLib
|
||||
IoLib
|
||||
PL390GicSecLib
|
||||
ArmGicSecLib
|
||||
PrintLib
|
||||
SerialPortLib
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue