mirror of https://github.com/acidanthera/audk.git
Add patch-able PCD to support binary modification of MRC module.
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17036 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
David Wei
zwei4
parent
359497b7a0
commit
567906c7b9
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@ -680,6 +680,126 @@
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# Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
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#######################################################################################################
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#
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# Begin of MRC parameters
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#
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## Memory Parameter Patchable.
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# FALSE - MRC Parameters are fixed for MinnowBoard Max<BR>
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# TRUE - MRC Parameters are patchable by following PCDs<BR>
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# @Prompt Memory Parameter Patchable.
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE
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## Memory Down or DIMM slot.
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# 0 - DIMM<BR>
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# 1 - Memory Down<BR>
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# @Prompt Enable Memory Down
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1
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## The speed of DRAM.
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# 0 - 800 MHz<BR>
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# 1 - 1066 MHz<BR>
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# 2 - 1333 MHz<BR>
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# 3 - 1600 MHz<BR>
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# @Prompt DRAM Speed
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# @ValidList 0x80000001 | 0, 1, 2, 3
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gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1
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## DRAM Type.
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# 0 - DDR3<BR>
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# 1 - DDR3L<BR>
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# 2 - DDR3U<BR>
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# 3 - DDR3All<BR>
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# 4 - LPDDR2<BR>
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# 5 - LPDDR3<BR>
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# 6 - DDR4<BR>
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# @Prompt DRAM Type
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# @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6
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gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1
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## Please populate DIMM slot 0 if only one DIMM is supported.
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# 0 - Disable<BR>
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# 1 - Enable<BR>
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# @Prompt DIMM 0 Enable
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1
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## DIMM 1 has to be identical to DIMM 0.
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# 0 - Disable<BR>
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# 1 - Enable<BR>
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# @Prompt DIMM 1 Enable Type
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0
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## DRAM device data width.
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# 0 - x8<BR>
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# 1 - x16<BR>
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# 2 - x32<BR>
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# @Prompt DIMM_DWIDTH
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# @ValidList 0x80000001 | 0, 1, 2
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gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1
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## DRAM device data density.
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# 0 - 1 Gbit<BR>
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# 1 - 2 Gbit<BR>
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# 2 - 4 Gbit<BR>
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# 3 - 8 Gbit<BR>
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# @Prompt DIMM_Density
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# @ValidList 0x80000001 | 0, 1, 2, 3
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gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2
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## DRAM device data bus width.
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# 0 - 8 bits<BR>
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# 1 - 16 bits<BR>
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# 2 - 32 bits<BR>
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# 3 - 64 bits<BR>
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# @Prompt DIMM_BusWidth
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# @ValidList 0x80000001 | 0, 1, 2, 3
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gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3
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## Ranks Per DIMM or Sides Per DIMM.
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# 0 - 1 Rank<BR>
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# 1 - 2 Ranks<BR>
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# @Prompt DIMM_Sides
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0
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## tCL.<BR><BR>
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# @Prompt tCL
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gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11
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## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc.
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# @Prompt tRP_tRCD
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gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11
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## tWR in DRAM clk.
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# @Prompt tWR
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gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12
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## tWTR in DRAM clk.
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# @Prompt tWTR
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gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6
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## tRRD in DRAM clk.
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# @Prompt tRRD
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gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6
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## tRTP in DRAM clk.
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# @Prompt tRTP
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gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6
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## tFAW in DRAM clk.
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# @Prompt tFAW
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gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32
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#
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# End of MRC parameters.
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#
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###############################################################################################
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[PcdsDynamicHii.common.DEFAULT]
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
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@ -680,6 +680,126 @@
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# Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
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#######################################################################################################
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#
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# Begin of MRC parameters
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#
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## Memory Parameter Patchable.
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# FALSE - MRC Parameters are fixed for MinnowBoard Max<BR>
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# TRUE - MRC Parameters are patchable by following PCDs<BR>
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# @Prompt Memory Parameter Patchable.
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE
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## Memory Down or DIMM slot.
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# 0 - DIMM<BR>
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# 1 - Memory Down<BR>
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# @Prompt Enable Memory Down
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1
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## The speed of DRAM.
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# 0 - 800 MHz<BR>
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# 1 - 1066 MHz<BR>
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# 2 - 1333 MHz<BR>
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# 3 - 1600 MHz<BR>
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# @Prompt DRAM Speed
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# @ValidList 0x80000001 | 0, 1, 2, 3
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gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1
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## DRAM Type.
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# 0 - DDR3<BR>
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# 1 - DDR3L<BR>
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# 2 - DDR3U<BR>
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# 3 - DDR3All<BR>
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# 4 - LPDDR2<BR>
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# 5 - LPDDR3<BR>
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# 6 - DDR4<BR>
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# @Prompt DRAM Type
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# @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6
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gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1
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## Please populate DIMM slot 0 if only one DIMM is supported.
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# 0 - Disable<BR>
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# 1 - Enable<BR>
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# @Prompt DIMM 0 Enable
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1
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## DIMM 1 has to be identical to DIMM 0.
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# 0 - Disable<BR>
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# 1 - Enable<BR>
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# @Prompt DIMM 1 Enable Type
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0
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## DRAM device data width.
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# 0 - x8<BR>
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# 1 - x16<BR>
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# 2 - x32<BR>
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# @Prompt DIMM_DWIDTH
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# @ValidList 0x80000001 | 0, 1, 2
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gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1
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## DRAM device data density.
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# 0 - 1 Gbit<BR>
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# 1 - 2 Gbit<BR>
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# 2 - 4 Gbit<BR>
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# 3 - 8 Gbit<BR>
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# @Prompt DIMM_Density
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# @ValidList 0x80000001 | 0, 1, 2, 3
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gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2
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## DRAM device data bus width.
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# 0 - 8 bits<BR>
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# 1 - 16 bits<BR>
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# 2 - 32 bits<BR>
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# 3 - 64 bits<BR>
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# @Prompt DIMM_BusWidth
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# @ValidList 0x80000001 | 0, 1, 2, 3
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gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3
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## Ranks Per DIMM or Sides Per DIMM.
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# 0 - 1 Rank<BR>
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# 1 - 2 Ranks<BR>
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# @Prompt DIMM_Sides
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0
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## tCL.<BR><BR>
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# @Prompt tCL
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gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11
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## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc.
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# @Prompt tRP_tRCD
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gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11
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## tWR in DRAM clk.
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# @Prompt tWR
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gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12
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## tWTR in DRAM clk.
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# @Prompt tWTR
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gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6
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## tRRD in DRAM clk.
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# @Prompt tRRD
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gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6
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## tRTP in DRAM clk.
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# @Prompt tRTP
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gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6
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## tFAW in DRAM clk.
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# @Prompt tFAW
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gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32
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#
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# End of MRC parameters.
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#
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###############################################################################################
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[PcdsDynamicHii.common.DEFAULT]
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
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@ -680,6 +680,126 @@
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# Note this PCD could be set to TRUE for best boot performance and set to FALSE for best device compatibility.
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdFastPS2Detection|TRUE
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#######################################################################################################
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#
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# Begin of MRC parameters
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#
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## Memory Parameter Patchable.
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# FALSE - MRC Parameters are fixed for MinnowBoard Max<BR>
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# TRUE - MRC Parameters are patchable by following PCDs<BR>
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# @Prompt Memory Parameter Patchable.
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|FALSE
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## Memory Down or DIMM slot.
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# 0 - DIMM<BR>
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# 1 - Memory Down<BR>
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# @Prompt Enable Memory Down
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|1
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## The speed of DRAM.
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# 0 - 800 MHz<BR>
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# 1 - 1066 MHz<BR>
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# 2 - 1333 MHz<BR>
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# 3 - 1600 MHz<BR>
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# @Prompt DRAM Speed
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# @ValidList 0x80000001 | 0, 1, 2, 3
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gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|1
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## DRAM Type.
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# 0 - DDR3<BR>
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# 1 - DDR3L<BR>
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# 2 - DDR3U<BR>
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# 3 - DDR3All<BR>
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# 4 - LPDDR2<BR>
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# 5 - LPDDR3<BR>
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# 6 - DDR4<BR>
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# @Prompt DRAM Type
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# @ValidList 0x80000001 | 0, 1, 2, 3, 4, 5, 6
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gVlvRefCodePkgTokenSpaceGuid.PcdDramType|1
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## Please populate DIMM slot 0 if only one DIMM is supported.
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# 0 - Disable<BR>
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# 1 - Enable<BR>
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# @Prompt DIMM 0 Enable
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|1
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## DIMM 1 has to be identical to DIMM 0.
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# 0 - Disable<BR>
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# 1 - Enable<BR>
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# @Prompt DIMM 1 Enable Type
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0
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## DRAM device data width.
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# 0 - x8<BR>
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# 1 - x16<BR>
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# 2 - x32<BR>
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# @Prompt DIMM_DWIDTH
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# @ValidList 0x80000001 | 0, 1, 2
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gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|1
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## DRAM device data density.
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# 0 - 1 Gbit<BR>
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# 1 - 2 Gbit<BR>
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# 2 - 4 Gbit<BR>
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# 3 - 8 Gbit<BR>
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# @Prompt DIMM_Density
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# @ValidList 0x80000001 | 0, 1, 2, 3
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gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|2
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## DRAM device data bus width.
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# 0 - 8 bits<BR>
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# 1 - 16 bits<BR>
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# 2 - 32 bits<BR>
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# 3 - 64 bits<BR>
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# @Prompt DIMM_BusWidth
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# @ValidList 0x80000001 | 0, 1, 2, 3
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gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|3
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## Ranks Per DIMM or Sides Per DIMM.
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# 0 - 1 Rank<BR>
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# 1 - 2 Ranks<BR>
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# @Prompt DIMM_Sides
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# @ValidList 0x80000001 | 0, 1
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gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0
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## tCL.<BR><BR>
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# @Prompt tCL
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gVlvRefCodePkgTokenSpaceGuid.PcdTcl|11
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## tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc.
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# @Prompt tRP_tRCD
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gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|11
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## tWR in DRAM clk.
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# @Prompt tWR
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gVlvRefCodePkgTokenSpaceGuid.PcdTwr|12
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## tWTR in DRAM clk.
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# @Prompt tWTR
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gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|6
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## tRRD in DRAM clk.
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# @Prompt tRRD
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gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|6
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## tRTP in DRAM clk.
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# @Prompt tRTP
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gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|6
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## tFAW in DRAM clk.
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# @Prompt tFAW
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gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|32
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#
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# End of MRC parameters.
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#
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###############################################################################################
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[PcdsDynamicHii.common.DEFAULT]
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
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gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
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