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Omap35xxPkg/Omap35xxTimerLib: Create a TimerConstructor in the TimerLib 

This constructor should be explicitely called by the Sec or PrePi phase
to initialize the OMAP353x timers.

This function is a copy of the Timer initialization function in BeagleBoardPkg/Sec.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11988 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-07-06 12:52:01 +00:00
parent 284ee2e829
commit 570d030a61
1 changed files with 32 additions and 1 deletions
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33
Omap35xxPkg/Library/Omap35xxTimerLib/TimerLib.c
View File

@ -12,7 +12,7 @@
**/
#include <Base.h>
#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/TimerLib.h>
@ -23,6 +23,37 @@
#include <Omap3530/Omap3530.h>
RETURN_STATUS
EFIAPI
TimerConstructor (
VOID
)
{
UINTN Timer = PcdGet32(PcdOmap35xxFreeTimer);
UINT32 TimerBaseAddress = TimerBase(Timer);
if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) {
// Set source clock for GPT3 & GPT4 to SYS_CLK
MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
// Set count & reload registers
MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
// Disable interrupts
MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
// Start Timer
MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
// Disable OMAP Watchdog timer (WDT2)
MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);
DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);
}
return EFI_SUCCESS;
}
UINTN
EFIAPI
MicroSecondDelay (