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UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmInitStack" with PatchInstructionX86()
Rename the variable to "gPatchSmmInitStack" so that its association with PatchInstructionX86() is clear from the declaration, change its type to X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(). This lets us remove the binary (DB) encoding of some instructions in "SmmInit.nasm". The size of the patched source operand is (sizeof (UINTN)). Cc: Eric Dong <eric.dong@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
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@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gPatchSmmCr3)
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global ASM_PFX(gPatchSmmCr3)
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global ASM_PFX(gPatchSmmCr4)
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global ASM_PFX(gPatchSmmCr4)
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global ASM_PFX(gPatchSmmCr0)
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global ASM_PFX(gPatchSmmCr0)
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global ASM_PFX(gSmmInitStack)
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global ASM_PFX(gPatchSmmInitStack)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitTemplate)
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global ASM_PFX(gcSmmInitTemplate)
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@ -72,8 +72,8 @@ BITS 32
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mov fs, edi
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mov fs, edi
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mov gs, edi
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mov gs, edi
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mov ss, edi
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mov ss, edi
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DB 0xbc ; mov esp, imm32
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mov esp, strict dword 0 ; source operand will be patched
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ASM_PFX(gSmmInitStack): DD 0
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ASM_PFX(gPatchSmmInitStack):
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call ASM_PFX(SmmInitHandler)
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call ASM_PFX(SmmInitHandler)
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rsm
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rsm
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@ -848,7 +848,11 @@ PiCpuSmmEntry (
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//
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//
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// Set SMI stack for SMM base relocation
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// Set SMI stack for SMM base relocation
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//
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//
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gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));
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PatchInstructionX86 (
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gPatchSmmInitStack,
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(UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)),
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sizeof (UINTN)
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);
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//
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//
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// Initialize IDT
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// Initialize IDT
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@ -302,7 +302,7 @@ extern UINT32 mSmmCr0;
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X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;
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X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr3;
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extern UINT32 mSmmCr4;
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extern UINT32 mSmmCr4;
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X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;
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X86_ASSEMBLY_PATCH_LABEL gPatchSmmCr4;
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extern UINTN gSmmInitStack;
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X86_ASSEMBLY_PATCH_LABEL gPatchSmmInitStack;
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/**
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/**
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Semaphore operation for all processor relocate SMMBase.
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Semaphore operation for all processor relocate SMMBase.
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@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
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global ASM_PFX(gPatchSmmCr3)
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global ASM_PFX(gPatchSmmCr3)
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global ASM_PFX(gPatchSmmCr4)
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global ASM_PFX(gPatchSmmCr4)
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global ASM_PFX(gPatchSmmCr0)
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global ASM_PFX(gPatchSmmCr0)
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global ASM_PFX(gSmmInitStack)
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global ASM_PFX(gPatchSmmInitStack)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmiInitGdtr)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitSize)
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global ASM_PFX(gcSmmInitTemplate)
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global ASM_PFX(gcSmmInitTemplate)
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@ -72,8 +72,8 @@ ASM_PFX(gPatchSmmCr0):
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BITS 64
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BITS 64
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@LongMode: ; long-mode starts here
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@LongMode: ; long-mode starts here
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DB 0x48, 0xbc ; mov rsp, imm64
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mov rsp, strict qword 0 ; source operand will be patched
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ASM_PFX(gSmmInitStack): DQ 0
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ASM_PFX(gPatchSmmInitStack):
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and sp, 0xfff0 ; make sure RSP is 16-byte aligned
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and sp, 0xfff0 ; make sure RSP is 16-byte aligned
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;
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;
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; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
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; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save
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