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MdeModulePkg/Core/DxeIplPeim: Add support for PCD PcdPteMemoryEncryptionAddressOrMask 

This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when creating page tables.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
This commit is contained in:
Leo Duran 2017-02-27 01:43:03 +08:00 committed by Star Zeng
parent e043f7895b
commit 5997daf742
4 changed files with 50 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
View File

@ -6,6 +6,8 @@
# needed to run the DXE Foundation. # needed to run the DXE Foundation.
# #
# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
#
# This program and the accompanying materials # This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License # are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at # which accompanies this distribution. The full text of the license may be found at
@ -112,6 +114,7 @@
[Pcd.IA32,Pcd.X64] [Pcd.IA32,Pcd.X64]
gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIMES_CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ## CONSUMES
[Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]
gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIMES_CONSUMES

12
MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
View File

@ -2,6 +2,8 @@
Ia32-specific functionality for DxeLoad. Ia32-specific functionality for DxeLoad.
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -82,6 +84,12 @@ Create4GPageTablesIa32Pae (
PAGE_TABLE_ENTRY *PageDirectoryEntry; PAGE_TABLE_ENTRY *PageDirectoryEntry;
UINTN TotalPagesNum; UINTN TotalPagesNum;
UINTN PageAddress; UINTN PageAddress;
UINT64 AddressEncMask;
//
// Make sure AddressEncMask is contained to smallest supported address field
//
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
PhysicalAddressBits = 32; PhysicalAddressBits = 32;
@ -111,7 +119,7 @@ Create4GPageTablesIa32Pae (
// //
// Fill in a Page Directory Pointer Entries // Fill in a Page Directory Pointer Entries
// //
PageDirectoryPointerEntry->Uint64 = (UINT64) (UINTN) PageDirectoryEntry; PageDirectoryPointerEntry->Uint64 = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask;
PageDirectoryPointerEntry->Bits.Present = 1; PageDirectoryPointerEntry->Bits.Present = 1;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += SIZE_2MB) { for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += SIZE_2MB) {
@ -124,7 +132,7 @@ Create4GPageTablesIa32Pae (
// //
// Fill in the Page Directory entries // Fill in the Page Directory entries
// //
PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress; PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress | AddressEncMask;
PageDirectoryEntry->Bits.ReadWrite = 1; PageDirectoryEntry->Bits.ReadWrite = 1;
PageDirectoryEntry->Bits.Present = 1; PageDirectoryEntry->Bits.Present = 1;
PageDirectoryEntry->Bits.MustBe1 = 1; PageDirectoryEntry->Bits.MustBe1 = 1;

39
MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
View File

@ -16,6 +16,8 @@
3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -29,6 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include "DxeIpl.h" #include "DxeIpl.h"
#include "VirtualMemory.h" #include "VirtualMemory.h"
/** /**
Enable Execute Disable Bit. Enable Execute Disable Bit.
@ -65,20 +68,27 @@ Split2MPageTo4K (
EFI_PHYSICAL_ADDRESS PhysicalAddress4K; EFI_PHYSICAL_ADDRESS PhysicalAddress4K;
UINTN IndexOfPageTableEntries; UINTN IndexOfPageTableEntries;
PAGE_TABLE_4K_ENTRY *PageTableEntry; PAGE_TABLE_4K_ENTRY *PageTableEntry;
UINT64 AddressEncMask;
//
// Make sure AddressEncMask is contained to smallest supported address field
//
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
PageTableEntry = AllocatePages (1); PageTableEntry = AllocatePages (1);
ASSERT (PageTableEntry != NULL); ASSERT (PageTableEntry != NULL);
// //
// Fill in 2M page entry. // Fill in 2M page entry.
// //
*PageEntry2M = (UINT64) (UINTN) PageTableEntry | IA32_PG_P | IA32_PG_RW; *PageEntry2M = (UINT64) (UINTN) PageTableEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
PhysicalAddress4K = PhysicalAddress; PhysicalAddress4K = PhysicalAddress;
for (IndexOfPageTableEntries = 0; IndexOfPageTableEntries < 512; IndexOfPageTableEntries++, PageTableEntry++, PhysicalAddress4K += SIZE_4KB) { for (IndexOfPageTableEntries = 0; IndexOfPageTableEntries < 512; IndexOfPageTableEntries++, PageTableEntry++, PhysicalAddress4K += SIZE_4KB) {
// //
// Fill in the Page Table entries // Fill in the Page Table entries
// //
PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K; PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;
PageTableEntry->Bits.ReadWrite = 1; PageTableEntry->Bits.ReadWrite = 1;
PageTableEntry->Bits.Present = 1; PageTableEntry->Bits.Present = 1;
if ((PhysicalAddress4K >= StackBase) && (PhysicalAddress4K < StackBase + StackSize)) { if ((PhysicalAddress4K >= StackBase) && (PhysicalAddress4K < StackBase + StackSize)) {
@ -110,13 +120,20 @@ Split1GPageTo2M (
EFI_PHYSICAL_ADDRESS PhysicalAddress2M; EFI_PHYSICAL_ADDRESS PhysicalAddress2M;
UINTN IndexOfPageDirectoryEntries; UINTN IndexOfPageDirectoryEntries;
PAGE_TABLE_ENTRY *PageDirectoryEntry; PAGE_TABLE_ENTRY *PageDirectoryEntry;
UINT64 AddressEncMask;
//
// Make sure AddressEncMask is contained to smallest supported address field
//
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
PageDirectoryEntry = AllocatePages (1); PageDirectoryEntry = AllocatePages (1);
ASSERT (PageDirectoryEntry != NULL); ASSERT (PageDirectoryEntry != NULL);
// //
// Fill in 1G page entry. // Fill in 1G page entry.
// //
*PageEntry1G = (UINT64) (UINTN) PageDirectoryEntry | IA32_PG_P | IA32_PG_RW; *PageEntry1G = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
PhysicalAddress2M = PhysicalAddress; PhysicalAddress2M = PhysicalAddress;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) { for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) {
@ -129,7 +146,7 @@ Split1GPageTo2M (
// //
// Fill in the Page Directory entries // Fill in the Page Directory entries
// //
PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress2M; PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress2M | AddressEncMask;
PageDirectoryEntry->Bits.ReadWrite = 1; PageDirectoryEntry->Bits.ReadWrite = 1;
PageDirectoryEntry->Bits.Present = 1; PageDirectoryEntry->Bits.Present = 1;
PageDirectoryEntry->Bits.MustBe1 = 1; PageDirectoryEntry->Bits.MustBe1 = 1;
@ -171,6 +188,12 @@ CreateIdentityMappingPageTables (
VOID *Hob; VOID *Hob;
BOOLEAN Page1GSupport; BOOLEAN Page1GSupport;
PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
UINT64 AddressEncMask;
//
// Make sure AddressEncMask is contained to smallest supported address field
//
AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
Page1GSupport = FALSE; Page1GSupport = FALSE;
if (PcdGetBool(PcdUse1GPageTable)) { if (PcdGetBool(PcdUse1GPageTable)) {
@ -248,7 +271,7 @@ CreateIdentityMappingPageTables (
// //
// Make a PML4 Entry // Make a PML4 Entry
// //
PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry; PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;
PageMapLevel4Entry->Bits.ReadWrite = 1; PageMapLevel4Entry->Bits.ReadWrite = 1;
PageMapLevel4Entry->Bits.Present = 1; PageMapLevel4Entry->Bits.Present = 1;
@ -262,7 +285,7 @@ CreateIdentityMappingPageTables (
// //
// Fill in the Page Directory entries // Fill in the Page Directory entries
// //
PageDirectory1GEntry->Uint64 = (UINT64)PageAddress; PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;
PageDirectory1GEntry->Bits.ReadWrite = 1; PageDirectory1GEntry->Bits.ReadWrite = 1;
PageDirectory1GEntry->Bits.Present = 1; PageDirectory1GEntry->Bits.Present = 1;
PageDirectory1GEntry->Bits.MustBe1 = 1; PageDirectory1GEntry->Bits.MustBe1 = 1;
@ -280,7 +303,7 @@ CreateIdentityMappingPageTables (
// //
// Fill in a Page Directory Pointer Entries // Fill in a Page Directory Pointer Entries
// //
PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry; PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;
PageDirectoryPointerEntry->Bits.ReadWrite = 1; PageDirectoryPointerEntry->Bits.ReadWrite = 1;
PageDirectoryPointerEntry->Bits.Present = 1; PageDirectoryPointerEntry->Bits.Present = 1;
@ -294,7 +317,7 @@ CreateIdentityMappingPageTables (
// //
// Fill in the Page Directory entries // Fill in the Page Directory entries
// //
PageDirectoryEntry->Uint64 = (UINT64)PageAddress; PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;
PageDirectoryEntry->Bits.ReadWrite = 1; PageDirectoryEntry->Bits.ReadWrite = 1;
PageDirectoryEntry->Bits.Present = 1; PageDirectoryEntry->Bits.Present = 1;
PageDirectoryEntry->Bits.MustBe1 = 1; PageDirectoryEntry->Bits.MustBe1 = 1;

5
MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h
View File

@ -8,6 +8,8 @@
4) AMD64 Architecture Programmer's Manual Volume 2: System Programming 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -23,6 +25,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define SYS_CODE64_SEL 0x38 #define SYS_CODE64_SEL 0x38
#pragma pack(1) #pragma pack(1)
typedef union { typedef union {
@ -148,6 +151,8 @@ typedef union {
#define IA32_PG_P BIT0 #define IA32_PG_P BIT0
#define IA32_PG_RW BIT1 #define IA32_PG_RW BIT1
#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
/** /**
Enable Execute Disable Bit. Enable Execute Disable Bit.