diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index e9e243ca05..173bbfcfcb 100644
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -281,7 +281,7 @@ SecStartupPhase2(
     // will be built based on them in PEI phase.
     //
     SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);
-    SecCoreData->PeiTemporaryRamSize &= ~0x07;
+    SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;
   } else {
     //
     // No addition PPI, PpiList directly point to the common PPI list.