mirror of https://github.com/acidanthera/audk.git
1. BaseSmbusLib: Make SmbusReadDataByte() & SmbusWriteBlock() function well by re-arranging register settings.
2. BaseMemoryLibMmx for X64: Make CopyMem() be reentrant by saving Mm0 to r10. 3. DxeCorePerformanceLib: Fix some typo to save build error of that library instance. 4. Remove the orphanage definition of gEfiPerformanceProtocolGuid git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@859 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
parent
9c091616cd
commit
5b1b9d8bf4
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@ -427,11 +427,6 @@
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<GuidValue>125F2DE1-FB85-440C-A54C-4D99358A8D38</GuidValue>
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<HelpText/>
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</Entry>
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<Entry Name="Performance">
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<C_Name>gEfiPerformanceProtocolGuid</C_Name>
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<GuidValue>FFECFFFF-923C-14D2-9E3F-22A0C969563B</GuidValue>
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<HelpText/>
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</Entry>
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<Entry Name="PxeDhcp4">
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<C_Name>gEfiPxeDhcp4ProtocolGuid</C_Name>
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<GuidValue>03C4E624-AC28-11D3-9A2D-0090293FC14D</GuidValue>
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@ -214,7 +214,6 @@ StartGauge (
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UINTN GaugeDataSize;
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UINTN OldGaugeDataSize;
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GAUGE_DATA_HEADER *OldGaugeData;
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EFI_STATUS Status;
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UINT32 Index;
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Index = mGaugeData->NumberOfEntries;
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@ -230,7 +229,7 @@ StartGauge (
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mGaugeData = AllocateZeroPool (GaugeDataSize);
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if (mGaugeData == NULL) {
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return EFI_OUT_OF_MEMORY;
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return EFI_OUT_OF_RESOURCES;
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}
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//
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// Initialize new data arry and migrate old data one.
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@ -425,7 +424,6 @@ DxeCorePerformanceLibConstructor (
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//
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// Install the protocol interfaces.
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//
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Handle = NULL;
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Status = gBS->InstallProtocolInterface (
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&mHandle,
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&gPerformanceProtocolGuid,
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@ -46,6 +46,9 @@
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<LibraryClass Usage="ALWAYS_CONSUMED">
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<Keyword>UefiBootServicesTableLib</Keyword>
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</LibraryClass>
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<LibraryClass Usage="ALWAYS_CONSUMED">
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<Keyword>MemoryAllocationLib</Keyword>
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</LibraryClass>
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</LibraryClassDefinitions>
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<SourceFiles>
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<Filename>DxeCorePerformanceLib.c</Filename>
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@ -46,6 +46,7 @@ InternalMemCopyMem PROC USES rsi rdi
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and r8, 7
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shr rcx, 3 ; rcx <- # of Qwords to copy
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jz @CopyBytes
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DB 49h, 0fh, 7eh, 0c2h ; movq r10, mm0 ; save mm0
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@@:
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DB 48h, 0fh, 6fh, 06h ; movq mm0, [rsi]
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DB 48h, 0fh, 0e7h, 07h ; movntq [rdi], mm0
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@ -53,6 +54,7 @@ InternalMemCopyMem PROC USES rsi rdi
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add rdi, 8
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loop @B
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mfence
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DB 49h, 0fh, 6eh, 0c2h ; movq mm0, r10 ; restore mm0
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jmp @CopyBytes
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@CopyBackward:
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mov rdi, r9 ; rdi <- End of Destination
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@ -25,10 +25,10 @@
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//
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// Replaced by PCD
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//
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#define ICH_SMBUS_BASE_ADDRESS 0xEFA0
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#define ICH_SMBUS_IO_BASE_ADDRESS 0xEFA0
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/**
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Reads an 8-bit SMBUS register on ICH.
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Reads an 8-bit register on ICH SMBUS controller.
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This internal function reads an SMBUS register specified by Offset.
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@ -42,11 +42,11 @@ InternalSmBusIoRead8 (
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IN UINTN Offset
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)
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{
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return IoRead8 (ICH_SMBUS_BASE_ADDRESS + Offset);
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return IoRead8 (ICH_SMBUS_IO_BASE_ADDRESS + Offset);
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}
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/**
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Writes an 8-bit SMBUS register on ICH.
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Writes an 8-bit register on ICH SMBUS controller.
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This internal function writes an SMBUS register specified by Offset.
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@ -62,7 +62,7 @@ InternalSmBusIoWrite8 (
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IN UINT8 Value
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)
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{
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return IoWrite8 (ICH_SMBUS_BASE_ADDRESS + Offset, Value);
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return IoWrite8 (ICH_SMBUS_IO_BASE_ADDRESS + Offset, Value);
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}
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/**
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@ -89,32 +89,30 @@ InternalSmBusAcquire (
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return RETURN_TIMEOUT;
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} else if ((HostStatus & SMBUS_B_HOST_BUSY) != 0) {
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//
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// Clear Status Register and exit
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// Clear host status register and exit.
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//
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InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);
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return RETURN_TIMEOUT;
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}
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//
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// Clear byte pointer of 32-byte buffer.
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// Clear out any odd status information (Will Not Clear In Use).
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//
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InternalSmBusIoRead8 (SMBUS_R_HST_CTL);
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//
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// Clear BYTE_DONE status
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//
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InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_BYTE_DONE_STS);
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InternalSmBusIoWrite8 (SMBUS_R_HST_STS, HostStatus);
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return RETURN_SUCCESS;
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}
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/**
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Waits until the completion of SMBUS transaction.
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Starts the SMBUS transaction and waits until the end.
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This internal function waits until the transaction of SMBUS is over
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by polling the INTR bit of Host status register.
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This internal function start the SMBUS transaction and waits until the transaction
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of SMBUS is over by polling the INTR bit of Host status register.
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If the SMBUS is not available, RETURN_TIMEOUT is returned;
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Otherwise, it performs some basic initializations and returns
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RETURN_SUCCESS.
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@param HostControl The Host control command to start SMBUS transaction.
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@retval RETURN_SUCCESS The SMBUS command was executed successfully.
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@retval RETURN_CRC_ERROR The checksum is not correct (PEC is incorrect).
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@retval RETURN_DEVICE_ERROR The request was not completed because a failure reflected
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@ -124,18 +122,21 @@ InternalSmBusAcquire (
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**/
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RETURN_STATUS
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InternalSmBusWait (
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VOID
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InternalSmBusStart (
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IN UINT8 HostControl
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)
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{
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UINT8 HostStatus;
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UINT8 AuxiliaryStatus;
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BOOLEAN First;
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First = TRUE;
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//
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// Set Host Control Register (Initiate Operation, Interrupt disabled).
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//
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InternalSmBusIoWrite8 (SMBUS_R_HST_CTL, HostControl + SMBUS_B_START);
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do {
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//
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// Poll INTR bit of host status register.
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// Poll INTR bit of Host Status Register.
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//
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HostStatus = InternalSmBusIoRead8 (SMBUS_R_HST_STS);
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} while ((HostStatus & (SMBUS_B_INTR | SMBUS_B_ERROR | SMBUS_B_BYTE_DONE_STS)) == 0);
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@ -144,11 +145,11 @@ InternalSmBusWait (
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return RETURN_SUCCESS;
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}
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//
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// Clear error bits of host status register
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// Clear error bits of Host Status Register.
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//
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InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_ERROR);
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//
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// Read auxiliary status register to judge CRC error.
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// Read Auxiliary Status Register to judge CRC error.
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//
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AuxiliaryStatus = InternalSmBusIoRead8 (SMBUS_R_AUX_STS);
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if ((AuxiliaryStatus & SMBUS_B_CRCE) != 0) {
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@ -159,64 +160,85 @@ InternalSmBusWait (
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}
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/**
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Executes an SMBUS quick read/write command.
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Executes an SMBUS quick, byte or word command.
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This internal function executes an SMBUS quick read/write command
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on the SMBUS device specified by SmBusAddress.
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Only the SMBUS slave address field of SmBusAddress is required.
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This internal function executes an SMBUS quick, byte or word commond.
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If Status is not NULL, then the status of the executed command is returned in Status.
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@param HostControl The value of Host Control Register to set.
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@param SmBusAddress Address that encodes the SMBUS Slave Address,
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SMBUS Command, SMBUS Data Length, and PEC.
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@param Value The byte/word write to the SMBUS.
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@param Status Return status for the executed command.
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This is an optional parameter and may be NULL.
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@return The byte/word read from the SMBUS.
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**/
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VOID
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EFIAPI
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InternalSmBusQuick (
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UINT16
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InternalSmBusNonBlock (
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IN UINT8 HostControl,
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IN UINTN SmBusAddress,
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OUT RETURN_STATUS *Status OPTIONAL
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IN UINT16 Value,
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OUT RETURN_STATUS *Status
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)
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{
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RETURN_STATUS ReturnStatus;
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UINT8 AuxiliaryControl;
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//
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// Try to acquire the ownership of ICH SMBUS.
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//
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ReturnStatus = InternalSmBusAcquire ();
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if (RETURN_ERROR (ReturnStatus)) {
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goto Done;
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}
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//
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// Set Command register
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// Set the appropriate Host Control Register and auxiliary Control Register.
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//
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InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, 0);
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AuxiliaryControl = 0;
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if (SMBUS_LIB_PEC (SmBusAddress)) {
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AuxiliaryControl |= SMBUS_B_AAC;
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HostControl |= SMBUS_B_PEC_EN;
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}
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//
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// Set Auxiliary Control register
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// Set Host Commond Register.
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//
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InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, 0);
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InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));
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//
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// Set SMBus slave address for the device to send/receive from
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// Write value to Host Data 0 and Host Data 1 Registers.
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//
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InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) Value);
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InternalSmBusIoWrite8 (SMBUS_R_HST_D1, (UINT8) (Value >> 8));
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//
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// Set Auxiliary Control Regiester.
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//
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InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, AuxiliaryControl);
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//
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// Set SMBUS slave address for the device to send/receive from.
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//
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InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);
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//
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// Set Control Register (Initiate Operation, Interrupt disabled)
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// Start the SMBUS transaction and wait for the end.
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//
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InternalSmBusIoWrite8 (SMBUS_R_HST_CTL, SMBUS_V_SMB_CMD_QUICK + SMBUS_B_START);
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ReturnStatus = InternalSmBusStart (HostControl);
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//
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// Wait for the end
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// Read value from Host Data 0 and Host Data 1 Registers.
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//
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ReturnStatus = InternalSmBusWait ();
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Value = InternalSmBusIoRead8 (SMBUS_R_HST_D1) << 8;
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Value |= InternalSmBusIoRead8 (SMBUS_R_HST_D0);
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//
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// Clear status register and exit
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// Clear Host Status Register and Auxiliary Status Register.
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//
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InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);;
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InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);
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InternalSmBusIoWrite8 (SMBUS_R_AUX_STS, SMBUS_B_CRCE);
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Done:
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if (Status != NULL) {
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*Status = ReturnStatus;
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}
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return Value;
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}
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/**
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@ -248,7 +270,12 @@ SmBusQuickRead (
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ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
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ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);
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InternalSmBusQuick (SmBusAddress | SMBUS_B_READ, Status);
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InternalSmBusNonBlock (
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SMBUS_V_SMB_CMD_QUICK,
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SmBusAddress | SMBUS_B_READ,
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0,
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Status
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);
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}
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/**
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|
@ -280,88 +307,12 @@ SmBusQuickWrite (
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ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
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ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);
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|
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InternalSmBusQuick (SmBusAddress | SMBUS_B_WRITE, Status);
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}
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/**
|
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Executes an SMBUS byte or word command.
|
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|
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This internal function executes an .
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Only the SMBUS slave address field of SmBusAddress is required.
|
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If Status is not NULL, then the status of the executed command is returned in Status.
|
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|
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@param HostControl The value of Host Control Register to set.
|
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@param SmBusAddress Address that encodes the SMBUS Slave Address,
|
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SMBUS Command, SMBUS Data Length, and PEC.
|
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@param Value The byte/word write to the SMBUS.
|
||||
@param Status Return status for the executed command.
|
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This is an optional parameter and may be NULL.
|
||||
|
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@return The byte/word read from the SMBUS.
|
||||
|
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**/
|
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UINT16
|
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InternalSmBusByteWord (
|
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IN UINT8 HostControl,
|
||||
IN UINTN SmBusAddress,
|
||||
IN UINT16 Value,
|
||||
OUT RETURN_STATUS *Status
|
||||
)
|
||||
{
|
||||
RETURN_STATUS ReturnStatus;
|
||||
UINT8 AuxiliaryControl;
|
||||
|
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ReturnStatus = InternalSmBusAcquire ();
|
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if (RETURN_ERROR (ReturnStatus)) {
|
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goto Done;
|
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}
|
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|
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AuxiliaryControl = 0;
|
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if (SMBUS_LIB_PEC (SmBusAddress)) {
|
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AuxiliaryControl |= SMBUS_B_AAC;
|
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HostControl |= SMBUS_B_PEC_EN;
|
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}
|
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//
|
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// Set commond register
|
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//
|
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InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));
|
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|
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InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) Value);
|
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InternalSmBusIoWrite8 (SMBUS_R_HST_D1, (UINT8) (Value >> 8));
|
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|
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//
|
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// Set Auxiliary Control Regiester.
|
||||
//
|
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InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, AuxiliaryControl);
|
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//
|
||||
// Set SMBus slave address for the device to send/receive from.
|
||||
//
|
||||
InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);
|
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//
|
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// Set Control Register (Initiate Operation, Interrupt disabled)
|
||||
//
|
||||
InternalSmBusIoWrite8 (SMBUS_R_HST_CTL, HostControl + SMBUS_B_START);
|
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|
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//
|
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// Wait for the end
|
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//
|
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ReturnStatus = InternalSmBusWait ();
|
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|
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Value = InternalSmBusIoRead8 (SMBUS_R_HST_D1) << 8;
|
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Value |= InternalSmBusIoRead8 (SMBUS_R_HST_D0);
|
||||
|
||||
//
|
||||
// Clear status register and exit
|
||||
//
|
||||
InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);;
|
||||
|
||||
Done:
|
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if (Status != NULL) {
|
||||
*Status = ReturnStatus;
|
||||
}
|
||||
|
||||
return Value;
|
||||
InternalSmBusNonBlock (
|
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SMBUS_V_SMB_CMD_QUICK,
|
||||
SmBusAddress | SMBUS_B_WRITE,
|
||||
0,
|
||||
Status
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -394,7 +345,7 @@ SmBusReceiveByte (
|
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ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
|
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ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);
|
||||
|
||||
return (UINT8) InternalSmBusByteWord (
|
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return (UINT8) InternalSmBusNonBlock (
|
||||
SMBUS_V_SMB_CMD_BYTE,
|
||||
SmBusAddress | SMBUS_B_READ,
|
||||
0,
|
||||
|
@ -434,7 +385,7 @@ SmBusSendByte (
|
|||
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
|
||||
ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);
|
||||
|
||||
return (UINT8) InternalSmBusByteWord (
|
||||
return (UINT8) InternalSmBusNonBlock (
|
||||
SMBUS_V_SMB_CMD_BYTE,
|
||||
SmBusAddress | SMBUS_B_WRITE,
|
||||
Value,
|
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|
@ -470,7 +421,7 @@ SmBusReadDataByte (
|
|||
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
|
||||
ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);
|
||||
|
||||
return (UINT8) InternalSmBusByteWord (
|
||||
return (UINT8) InternalSmBusNonBlock (
|
||||
SMBUS_V_SMB_CMD_BYTE_DATA,
|
||||
SmBusAddress | SMBUS_B_READ,
|
||||
0,
|
||||
|
@ -509,7 +460,7 @@ SmBusWriteDataByte (
|
|||
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
|
||||
ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);
|
||||
|
||||
return (UINT8) InternalSmBusByteWord (
|
||||
return (UINT8) InternalSmBusNonBlock (
|
||||
SMBUS_V_SMB_CMD_BYTE_DATA,
|
||||
SmBusAddress | SMBUS_B_WRITE,
|
||||
Value,
|
||||
|
@ -545,7 +496,7 @@ SmBusReadDataWord (
|
|||
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
|
||||
ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);
|
||||
|
||||
return InternalSmBusByteWord (
|
||||
return InternalSmBusNonBlock (
|
||||
SMBUS_V_SMB_CMD_WORD_DATA,
|
||||
SmBusAddress | SMBUS_B_READ,
|
||||
0,
|
||||
|
@ -584,7 +535,7 @@ SmBusWriteDataWord (
|
|||
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
|
||||
ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);
|
||||
|
||||
return InternalSmBusByteWord (
|
||||
return InternalSmBusNonBlock (
|
||||
SMBUS_V_SMB_CMD_WORD_DATA,
|
||||
SmBusAddress | SMBUS_B_WRITE,
|
||||
Value,
|
||||
|
@ -623,7 +574,7 @@ SmBusProcessCall (
|
|||
ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) == 0);
|
||||
ASSERT (SMBUS_LIB_RESEARVED (SmBusAddress) == 0);
|
||||
|
||||
return InternalSmBusByteWord (
|
||||
return InternalSmBusNonBlock (
|
||||
SMBUS_V_SMB_CMD_PROCESS_CALL,
|
||||
SmBusAddress | SMBUS_B_WRITE,
|
||||
Value,
|
||||
|
@ -668,59 +619,75 @@ InternalSmBusBlock (
|
|||
UINT8 AuxiliaryControl;
|
||||
|
||||
BytesCount = SMBUS_LIB_LENGTH (SmBusAddress);
|
||||
|
||||
//
|
||||
// Try to acquire the ownership of ICH SMBUS.
|
||||
//
|
||||
ReturnStatus = InternalSmBusAcquire ();
|
||||
if (RETURN_ERROR (ReturnStatus)) {
|
||||
goto Done;
|
||||
}
|
||||
|
||||
//
|
||||
// Set the appropriate Host Control Register and auxiliary Control Register.
|
||||
//
|
||||
AuxiliaryControl = SMBUS_B_E32B;
|
||||
if (SMBUS_LIB_PEC (SmBusAddress)) {
|
||||
AuxiliaryControl |= SMBUS_B_AAC;
|
||||
HostControl |= SMBUS_B_PEC_EN;
|
||||
}
|
||||
|
||||
//
|
||||
// Set Host Command Register.
|
||||
//
|
||||
InternalSmBusIoWrite8 (SMBUS_R_HST_CMD, (UINT8) SMBUS_LIB_COMMAND (SmBusAddress));
|
||||
|
||||
InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) BytesCount);
|
||||
|
||||
if (WriteBuffer != NULL) {
|
||||
for (Index = 0; Index < BytesCount; Index++) {
|
||||
InternalSmBusIoWrite8 (SMBUS_R_HOST_BLOCK_DB, WriteBuffer[Index]);
|
||||
}
|
||||
}
|
||||
//
|
||||
// Set Auxiliary Control Regiester.
|
||||
//
|
||||
InternalSmBusIoWrite8 (SMBUS_R_AUX_CTL, AuxiliaryControl);
|
||||
//
|
||||
// Set SMBus slave address for the device to send/receive from
|
||||
// Clear byte pointer of 32-byte buffer.
|
||||
//
|
||||
InternalSmBusIoRead8 (SMBUS_R_HST_CTL);
|
||||
|
||||
if (WriteBuffer != NULL) {
|
||||
//
|
||||
// Write the number of block to Host Block Data Byte Register.
|
||||
//
|
||||
InternalSmBusIoWrite8 (SMBUS_R_HST_D0, (UINT8) BytesCount);
|
||||
//
|
||||
// Write data block to Host Block Data Register.
|
||||
//
|
||||
for (Index = 0; Index < BytesCount; Index++) {
|
||||
InternalSmBusIoWrite8 (SMBUS_R_HOST_BLOCK_DB, WriteBuffer[Index]);
|
||||
}
|
||||
}
|
||||
//
|
||||
// Set SMBUS slave address for the device to send/receive from.
|
||||
//
|
||||
InternalSmBusIoWrite8 (SMBUS_R_XMIT_SLVA, (UINT8) SmBusAddress);
|
||||
//
|
||||
// Set Control Register (Initiate Operation, Interrupt disabled)
|
||||
// Start the SMBUS transaction and wait for the end.
|
||||
//
|
||||
InternalSmBusIoWrite8 (SMBUS_R_HST_CTL, HostControl + SMBUS_B_START);
|
||||
|
||||
//
|
||||
// Wait for the end
|
||||
//
|
||||
ReturnStatus = InternalSmBusWait ();
|
||||
ReturnStatus = InternalSmBusStart (HostControl);
|
||||
if (RETURN_ERROR (ReturnStatus)) {
|
||||
goto Done;
|
||||
}
|
||||
|
||||
BytesCount = InternalSmBusIoRead8 (SMBUS_R_HST_D0);
|
||||
if (ReadBuffer != NULL) {
|
||||
//
|
||||
// Read the number of block from host block data byte register.
|
||||
//
|
||||
BytesCount = InternalSmBusIoRead8 (SMBUS_R_HST_D0);
|
||||
//
|
||||
// Write data block from Host Block Data Register.
|
||||
//
|
||||
for (Index = 0; Index < BytesCount; Index++) {
|
||||
ReadBuffer[Index] = InternalSmBusIoRead8 (SMBUS_R_HOST_BLOCK_DB);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Clear status register and exit
|
||||
// Clear Host Status Register and Auxiliary Status Register.
|
||||
//
|
||||
InternalSmBusIoWrite8 (SMBUS_R_HST_STS, SMBUS_B_HSTS_ALL);
|
||||
InternalSmBusIoWrite8 (SMBUS_R_AUX_STS, SMBUS_B_CRCE);
|
||||
|
||||
Done:
|
||||
if (Status != NULL) {
|
||||
|
|
Loading…
Reference in New Issue