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OvmfPkg: widen PcdQ35TsegMbytes to UINT16 

Widen PcdQ35TsegMbytes to UINT16, in preparation for setting it
dynamically to the QEMU-advertized extended TSEG size (which is 16-bits
wide).

Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Laszlo Ersek 2017-07-04 12:27:24 +02:00
parent 253d81c71f
commit 5b31f660c9
3 changed files with 7 additions and 7 deletions
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2
OvmfPkg/OvmfPkg.dec
View File

@ -95,7 +95,7 @@
# undefined behavior.
#
# This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below).
gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT8|0x20
gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9

6
OvmfPkg/PlatformPei/MemDetect.c
View File

@ -348,7 +348,7 @@ PublishPeiMemory (
//
// TSEG is chipped from the end of low RAM
//
LowerMemorySize -= FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;
LowerMemorySize -= FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB;
}
//
@ -456,7 +456,7 @@ QemuInitializeRam (
if (FeaturePcdGet (PcdSmmSmramRequire)) {
UINT32 TsegSize;
TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;
TsegSize = FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB;
AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);
AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,
TRUE);
@ -605,7 +605,7 @@ InitializeRamRegions (
// Make sure the TSEG area that we reported as a reserved memory resource
// cannot be used for reserved memory allocations.
//
TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;
TsegSize = FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB;
BuildMemoryAllocationHob (
GetSystemMemorySizeBelow4gb() - TsegSize,
TsegSize,

6
OvmfPkg/SmmAccess/SmmAccessPei.c
View File

@ -319,7 +319,7 @@ SmmAccessPeiEntryPoint (
// Set TSEG Memory Base.
//
PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB),
(TopOfLowRamMb - FixedPcdGet8 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHIFT);
(TopOfLowRamMb - FixedPcdGet16 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHIFT);
//
// Set TSEG size, and disable TSEG visibility outside of SMM. Note that the
@ -327,8 +327,8 @@ SmmAccessPeiEntryPoint (
// *restricted* to SMM.
//
EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;
EsmramcVal |= FixedPcdGet8 (PcdQ35TsegMbytes) == 8 ? MCH_ESMRAMC_TSEG_8MB :
FixedPcdGet8 (PcdQ35TsegMbytes) == 2 ? MCH_ESMRAMC_TSEG_2MB :
EsmramcVal |= FixedPcdGet16 (PcdQ35TsegMbytes) == 8 ? MCH_ESMRAMC_TSEG_8MB :
FixedPcdGet16 (PcdQ35TsegMbytes) == 2 ? MCH_ESMRAMC_TSEG_2MB :
MCH_ESMRAMC_TSEG_1MB;
EsmramcVal |= MCH_ESMRAMC_T_EN;
PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);