mirror of
https://github.com/acidanthera/audk.git
synced 2025-07-27 07:34:06 +02:00
MdePkg: PciExpressLib support variable size MMCONF
Add support for arbitrary sized MMCONF by introducing a new PCD. Add a return value to point out invalid PCI addresses. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <marcello.bauer@9elements.com> Cc: Patrick Rudolph <patrick.rudolph@9elements.com> Cc: Christian Walter <christian.walter@9elements.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
parent
28d7eea97e
commit
5c06585528
@ -2,8 +2,9 @@
|
|||||||
Provides services to access PCI Configuration Space using the MMIO PCI Express window.
|
Provides services to access PCI Configuration Space using the MMIO PCI Express window.
|
||||||
|
|
||||||
This library is identical to the PCI Library, except the access method for performing PCI
|
This library is identical to the PCI Library, except the access method for performing PCI
|
||||||
configuration cycles must be through the 256 MB PCI Express MMIO window whose base address
|
configuration cycles must be through the PCI Express MMIO window whose base address
|
||||||
is defined by PcdPciExpressBaseAddress.
|
is defined by PcdPciExpressBaseAddress and size defined by PcdPciExpressBaseSize.
|
||||||
|
|
||||||
|
|
||||||
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
|
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||||
|
@ -1,7 +1,7 @@
|
|||||||
## @file
|
## @file
|
||||||
# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
|
# Instance of PCI Express Library using the variable size PCI Express MMIO window.
|
||||||
#
|
#
|
||||||
# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
|
# PCI Express Library that uses the variable size PCI Express MMIO window to perform
|
||||||
# PCI Configuration cycles. Layers on top of an I/O Library instance.
|
# PCI Configuration cycles. Layers on top of an I/O Library instance.
|
||||||
#
|
#
|
||||||
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
|
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
|
||||||
@ -38,4 +38,4 @@
|
|||||||
|
|
||||||
[Pcd]
|
[Pcd]
|
||||||
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
|
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
|
||||||
|
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES
|
||||||
|
@ -22,7 +22,8 @@
|
|||||||
|
|
||||||
/**
|
/**
|
||||||
Assert the validity of a PCI address. A valid PCI address should contain 1's
|
Assert the validity of a PCI address. A valid PCI address should contain 1's
|
||||||
only in the low 28 bits.
|
only in the low 28 bits. PcdPciExpressBaseSize limits the size to the real
|
||||||
|
number of PCI busses in this segment.
|
||||||
|
|
||||||
@param A The address to validate.
|
@param A The address to validate.
|
||||||
|
|
||||||
@ -79,6 +80,24 @@ GetPciExpressBaseAddress (
|
|||||||
return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);
|
return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
Gets the size of PCI Express.
|
||||||
|
|
||||||
|
This internal functions retrieves PCI Express Base Size via a PCD entry
|
||||||
|
PcdPciExpressBaseSize.
|
||||||
|
|
||||||
|
@return The base size of PCI Express.
|
||||||
|
|
||||||
|
**/
|
||||||
|
STATIC
|
||||||
|
UINTN
|
||||||
|
PcdPciExpressBaseSize (
|
||||||
|
VOID
|
||||||
|
)
|
||||||
|
{
|
||||||
|
return (UINTN) PcdGet64 (PcdPciExpressBaseSize);
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
Reads an 8-bit PCI configuration register.
|
Reads an 8-bit PCI configuration register.
|
||||||
|
|
||||||
@ -91,7 +110,8 @@ GetPciExpressBaseAddress (
|
|||||||
@param Address The address that encodes the PCI Bus, Device, Function and
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||||||
Register.
|
Register.
|
||||||
|
|
||||||
@return The read value from the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The read value from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -101,6 +121,9 @@ PciExpressRead8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);
|
return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -117,7 +140,8 @@ PciExpressRead8 (
|
|||||||
Register.
|
Register.
|
||||||
@param Value The value to write.
|
@param Value The value to write.
|
||||||
|
|
||||||
@return The value written to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -128,6 +152,9 @@ PciExpressWrite8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
|
return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -148,7 +175,8 @@ PciExpressWrite8 (
|
|||||||
Register.
|
Register.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -159,6 +187,9 @@ PciExpressOr8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
|
return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -179,7 +210,8 @@ PciExpressOr8 (
|
|||||||
Register.
|
Register.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -190,6 +222,9 @@ PciExpressAnd8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
|
return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -212,7 +247,8 @@ PciExpressAnd8 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -224,6 +260,9 @@ PciExpressAndThenOr8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioAndThenOr8 (
|
return MmioAndThenOr8 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
AndData,
|
AndData,
|
||||||
@ -249,7 +288,9 @@ PciExpressAndThenOr8 (
|
|||||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||||
Range 0..7.
|
Range 0..7.
|
||||||
|
|
||||||
@return The value of the bit field read from the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value of the bit field read from the PCI configuration
|
||||||
|
register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -261,6 +302,9 @@ PciExpressBitFieldRead8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldRead8 (
|
return MmioBitFieldRead8 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -289,7 +333,8 @@ PciExpressBitFieldRead8 (
|
|||||||
Range 0..7.
|
Range 0..7.
|
||||||
@param Value The new value of the bit field.
|
@param Value The new value of the bit field.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -302,6 +347,9 @@ PciExpressBitFieldWrite8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldWrite8 (
|
return MmioBitFieldWrite8 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -334,7 +382,8 @@ PciExpressBitFieldWrite8 (
|
|||||||
Range 0..7.
|
Range 0..7.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -347,6 +396,9 @@ PciExpressBitFieldOr8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldOr8 (
|
return MmioBitFieldOr8 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -379,7 +431,8 @@ PciExpressBitFieldOr8 (
|
|||||||
Range 0..7.
|
Range 0..7.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -392,6 +445,9 @@ PciExpressBitFieldAnd8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAnd8 (
|
return MmioBitFieldAnd8 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -428,7 +484,8 @@ PciExpressBitFieldAnd8 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -442,6 +499,9 @@ PciExpressBitFieldAndThenOr8 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAndThenOr8 (
|
return MmioBitFieldAndThenOr8 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -464,7 +524,8 @@ PciExpressBitFieldAndThenOr8 (
|
|||||||
@param Address The address that encodes the PCI Bus, Device, Function and
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||||||
Register.
|
Register.
|
||||||
|
|
||||||
@return The read value from the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The read value from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -474,6 +535,9 @@ PciExpressRead16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);
|
return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -491,7 +555,8 @@ PciExpressRead16 (
|
|||||||
Register.
|
Register.
|
||||||
@param Value The value to write.
|
@param Value The value to write.
|
||||||
|
|
||||||
@return The value written to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -502,6 +567,9 @@ PciExpressWrite16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
|
return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -523,7 +591,8 @@ PciExpressWrite16 (
|
|||||||
Register.
|
Register.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -534,6 +603,9 @@ PciExpressOr16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
|
return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -555,7 +627,8 @@ PciExpressOr16 (
|
|||||||
Register.
|
Register.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -566,6 +639,9 @@ PciExpressAnd16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
|
return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -589,7 +665,8 @@ PciExpressAnd16 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -601,6 +678,9 @@ PciExpressAndThenOr16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioAndThenOr16 (
|
return MmioAndThenOr16 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
AndData,
|
AndData,
|
||||||
@ -627,7 +707,9 @@ PciExpressAndThenOr16 (
|
|||||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||||
Range 0..15.
|
Range 0..15.
|
||||||
|
|
||||||
@return The value of the bit field read from the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value of the bit field read from the PCI configuration
|
||||||
|
register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -639,6 +721,9 @@ PciExpressBitFieldRead16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldRead16 (
|
return MmioBitFieldRead16 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -668,7 +753,8 @@ PciExpressBitFieldRead16 (
|
|||||||
Range 0..15.
|
Range 0..15.
|
||||||
@param Value The new value of the bit field.
|
@param Value The new value of the bit field.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -681,6 +767,9 @@ PciExpressBitFieldWrite16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldWrite16 (
|
return MmioBitFieldWrite16 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -714,7 +803,8 @@ PciExpressBitFieldWrite16 (
|
|||||||
Range 0..15.
|
Range 0..15.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -727,6 +817,9 @@ PciExpressBitFieldOr16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldOr16 (
|
return MmioBitFieldOr16 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -760,7 +853,8 @@ PciExpressBitFieldOr16 (
|
|||||||
Range 0..15.
|
Range 0..15.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -773,6 +867,9 @@ PciExpressBitFieldAnd16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAnd16 (
|
return MmioBitFieldAnd16 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -810,7 +907,8 @@ PciExpressBitFieldAnd16 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -824,6 +922,9 @@ PciExpressBitFieldAndThenOr16 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAndThenOr16 (
|
return MmioBitFieldAndThenOr16 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -846,7 +947,8 @@ PciExpressBitFieldAndThenOr16 (
|
|||||||
@param Address The address that encodes the PCI Bus, Device, Function and
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||||||
Register.
|
Register.
|
||||||
|
|
||||||
@return The read value from the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The read value from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -856,6 +958,9 @@ PciExpressRead32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);
|
return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -873,7 +978,8 @@ PciExpressRead32 (
|
|||||||
Register.
|
Register.
|
||||||
@param Value The value to write.
|
@param Value The value to write.
|
||||||
|
|
||||||
@return The value written to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -884,6 +990,9 @@ PciExpressWrite32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
|
return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -905,7 +1014,8 @@ PciExpressWrite32 (
|
|||||||
Register.
|
Register.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -916,6 +1026,9 @@ PciExpressOr32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
|
return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -937,7 +1050,8 @@ PciExpressOr32 (
|
|||||||
Register.
|
Register.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -948,6 +1062,9 @@ PciExpressAnd32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
|
return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -971,7 +1088,8 @@ PciExpressAnd32 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -983,6 +1101,9 @@ PciExpressAndThenOr32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioAndThenOr32 (
|
return MmioAndThenOr32 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
AndData,
|
AndData,
|
||||||
@ -1009,7 +1130,9 @@ PciExpressAndThenOr32 (
|
|||||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||||
Range 0..31.
|
Range 0..31.
|
||||||
|
|
||||||
@return The value of the bit field read from the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value of the bit field read from the PCI
|
||||||
|
configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1021,6 +1144,9 @@ PciExpressBitFieldRead32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldRead32 (
|
return MmioBitFieldRead32 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1050,7 +1176,8 @@ PciExpressBitFieldRead32 (
|
|||||||
Range 0..31.
|
Range 0..31.
|
||||||
@param Value The new value of the bit field.
|
@param Value The new value of the bit field.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1063,6 +1190,9 @@ PciExpressBitFieldWrite32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldWrite32 (
|
return MmioBitFieldWrite32 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1096,7 +1226,8 @@ PciExpressBitFieldWrite32 (
|
|||||||
Range 0..31.
|
Range 0..31.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1109,6 +1240,9 @@ PciExpressBitFieldOr32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldOr32 (
|
return MmioBitFieldOr32 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1142,7 +1276,8 @@ PciExpressBitFieldOr32 (
|
|||||||
Range 0..31.
|
Range 0..31.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1155,6 +1290,9 @@ PciExpressBitFieldAnd32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAnd32 (
|
return MmioBitFieldAnd32 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1192,7 +1330,8 @@ PciExpressBitFieldAnd32 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1206,6 +1345,9 @@ PciExpressBitFieldAndThenOr32 (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAndThenOr32 (
|
return MmioBitFieldAndThenOr32 (
|
||||||
(UINTN) GetPciExpressBaseAddress () + Address,
|
(UINTN) GetPciExpressBaseAddress () + Address,
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1235,7 +1377,8 @@ PciExpressBitFieldAndThenOr32 (
|
|||||||
@param Size The size in bytes of the transfer.
|
@param Size The size in bytes of the transfer.
|
||||||
@param Buffer The pointer to a buffer receiving the data read.
|
@param Buffer The pointer to a buffer receiving the data read.
|
||||||
|
|
||||||
@return Size read data from StartAddress.
|
@retval (UINTN)-1 Invalid PCI address.
|
||||||
|
@retval other Size read data from StartAddress.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINTN
|
UINTN
|
||||||
@ -1249,6 +1392,9 @@ PciExpressReadBuffer (
|
|||||||
UINTN ReturnValue;
|
UINTN ReturnValue;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
||||||
|
if (StartAddress >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINTN) -1;
|
||||||
|
}
|
||||||
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
||||||
|
|
||||||
if (Size == 0) {
|
if (Size == 0) {
|
||||||
@ -1335,7 +1481,8 @@ PciExpressReadBuffer (
|
|||||||
@param Size The size in bytes of the transfer.
|
@param Size The size in bytes of the transfer.
|
||||||
@param Buffer The pointer to a buffer containing the data to write.
|
@param Buffer The pointer to a buffer containing the data to write.
|
||||||
|
|
||||||
@return Size written to StartAddress.
|
@retval (UINTN)-1 Invalid PCI address.
|
||||||
|
@retval other Size written to StartAddress.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINTN
|
UINTN
|
||||||
@ -1349,6 +1496,9 @@ PciExpressWriteBuffer (
|
|||||||
UINTN ReturnValue;
|
UINTN ReturnValue;
|
||||||
|
|
||||||
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
||||||
|
if (StartAddress >= PcdPciExpressBaseSize()) {
|
||||||
|
return (UINTN) -1;
|
||||||
|
}
|
||||||
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
||||||
|
|
||||||
if (Size == 0) {
|
if (Size == 0) {
|
||||||
|
@ -47,3 +47,4 @@
|
|||||||
|
|
||||||
[Pcd]
|
[Pcd]
|
||||||
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
|
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
|
||||||
|
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES
|
||||||
|
@ -25,6 +25,16 @@
|
|||||||
#include <Library/DxeServicesTableLib.h>
|
#include <Library/DxeServicesTableLib.h>
|
||||||
#include <Library/UefiRuntimeLib.h>
|
#include <Library/UefiRuntimeLib.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
Assert the validity of a PCI address. A valid PCI address should contain 1's
|
||||||
|
only in the low 28 bits.
|
||||||
|
|
||||||
|
@param A The address to validate.
|
||||||
|
|
||||||
|
**/
|
||||||
|
#define ASSERT_INVALID_PCI_ADDRESS(A) \
|
||||||
|
ASSERT (((A) & ~0xfffffff) == 0)
|
||||||
|
|
||||||
///
|
///
|
||||||
/// Define table for mapping PCI Express MMIO physical addresses to virtual addresses at OS runtime
|
/// Define table for mapping PCI Express MMIO physical addresses to virtual addresses at OS runtime
|
||||||
///
|
///
|
||||||
@ -39,9 +49,10 @@ typedef struct {
|
|||||||
EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;
|
EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;
|
||||||
|
|
||||||
///
|
///
|
||||||
/// Module global that contains the base physical address of the PCI Express MMIO range.
|
/// Module global that contains the base physical address and size of the PCI Express MMIO range.
|
||||||
///
|
///
|
||||||
UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;
|
UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;
|
||||||
|
UINTN mDxeRuntimePciExpressLibPciExpressBaseSize = 0;
|
||||||
|
|
||||||
///
|
///
|
||||||
/// The number of PCI devices that have been registered for runtime access.
|
/// The number of PCI devices that have been registered for runtime access.
|
||||||
@ -120,6 +131,7 @@ DxeRuntimePciExpressLibConstructor (
|
|||||||
// Cache the physical address of the PCI Express MMIO range into a module global variable
|
// Cache the physical address of the PCI Express MMIO range into a module global variable
|
||||||
//
|
//
|
||||||
mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
|
mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
|
||||||
|
mDxeRuntimePciExpressLibPciExpressBaseSize = (UINTN) PcdGet64 (PcdPciExpressBaseSize);
|
||||||
|
|
||||||
//
|
//
|
||||||
// Register SetVirtualAddressMap () notify function
|
// Register SetVirtualAddressMap () notify function
|
||||||
@ -179,8 +191,12 @@ DxeRuntimePciExpressLibDestructor (
|
|||||||
This internal functions retrieves PCI Express Base Address via a PCD entry
|
This internal functions retrieves PCI Express Base Address via a PCD entry
|
||||||
PcdPciExpressBaseAddress.
|
PcdPciExpressBaseAddress.
|
||||||
|
|
||||||
|
If Address > 0x0FFFFFFF, then ASSERT().
|
||||||
|
|
||||||
@param Address The address that encodes the PCI Bus, Device, Function and Register.
|
@param Address The address that encodes the PCI Bus, Device, Function and Register.
|
||||||
@return The base address of PCI Express.
|
|
||||||
|
@retval (UINTN)-1 Invalid PCI address.
|
||||||
|
@retval other The base address of PCI Express.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINTN
|
UINTN
|
||||||
@ -193,7 +209,14 @@ GetPciExpressAddress (
|
|||||||
//
|
//
|
||||||
// Make sure Address is valid
|
// Make sure Address is valid
|
||||||
//
|
//
|
||||||
ASSERT (((Address) & ~0xfffffff) == 0);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Make sure the Address is in MMCONF address space
|
||||||
|
//
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINTN) -1;
|
||||||
|
}
|
||||||
|
|
||||||
//
|
//
|
||||||
// Convert Address to a physical address in the MMIO PCI Express range
|
// Convert Address to a physical address in the MMIO PCI Express range
|
||||||
@ -236,7 +259,6 @@ GetPciExpressAddress (
|
|||||||
//
|
//
|
||||||
// No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.
|
// No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.
|
||||||
//
|
//
|
||||||
ASSERT (FALSE);
|
|
||||||
CpuBreakpoint();
|
CpuBreakpoint();
|
||||||
|
|
||||||
//
|
//
|
||||||
@ -288,7 +310,14 @@ PciExpressRegisterForRuntimeAccess (
|
|||||||
//
|
//
|
||||||
// Make sure Address is valid
|
// Make sure Address is valid
|
||||||
//
|
//
|
||||||
ASSERT (((Address) & ~0xfffffff) == 0);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Make sure the Address is in MMCONF address space
|
||||||
|
//
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return RETURN_UNSUPPORTED;
|
||||||
|
}
|
||||||
|
|
||||||
//
|
//
|
||||||
// Convert Address to a physical address in the MMIO PCI Express range
|
// Convert Address to a physical address in the MMIO PCI Express range
|
||||||
@ -354,8 +383,8 @@ PciExpressRegisterForRuntimeAccess (
|
|||||||
|
|
||||||
@param Address The address that encodes the PCI Bus, Device, Function and
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||||||
Register.
|
Register.
|
||||||
|
@retval 0xFF Invalid PCI address.
|
||||||
@return The read value from the PCI configuration register.
|
@retval other The read value from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -364,6 +393,10 @@ PciExpressRead8 (
|
|||||||
IN UINTN Address
|
IN UINTN Address
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioRead8 (GetPciExpressAddress (Address));
|
return MmioRead8 (GetPciExpressAddress (Address));
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -380,7 +413,8 @@ PciExpressRead8 (
|
|||||||
Register.
|
Register.
|
||||||
@param Value The value to write.
|
@param Value The value to write.
|
||||||
|
|
||||||
@return The value written to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -390,6 +424,9 @@ PciExpressWrite8 (
|
|||||||
IN UINT8 Value
|
IN UINT8 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioWrite8 (GetPciExpressAddress (Address), Value);
|
return MmioWrite8 (GetPciExpressAddress (Address), Value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -410,7 +447,8 @@ PciExpressWrite8 (
|
|||||||
Register.
|
Register.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -420,6 +458,9 @@ PciExpressOr8 (
|
|||||||
IN UINT8 OrData
|
IN UINT8 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioOr8 (GetPciExpressAddress (Address), OrData);
|
return MmioOr8 (GetPciExpressAddress (Address), OrData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -440,7 +481,8 @@ PciExpressOr8 (
|
|||||||
Register.
|
Register.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -450,6 +492,9 @@ PciExpressAnd8 (
|
|||||||
IN UINT8 AndData
|
IN UINT8 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioAnd8 (GetPciExpressAddress (Address), AndData);
|
return MmioAnd8 (GetPciExpressAddress (Address), AndData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -472,7 +517,8 @@ PciExpressAnd8 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -483,6 +529,9 @@ PciExpressAndThenOr8 (
|
|||||||
IN UINT8 OrData
|
IN UINT8 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioAndThenOr8 (
|
return MmioAndThenOr8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
AndData,
|
AndData,
|
||||||
@ -508,7 +557,8 @@ PciExpressAndThenOr8 (
|
|||||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||||
Range 0..7.
|
Range 0..7.
|
||||||
|
|
||||||
@return The value of the bit field read from the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value of the bit field read from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -519,6 +569,9 @@ PciExpressBitFieldRead8 (
|
|||||||
IN UINTN EndBit
|
IN UINTN EndBit
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldRead8 (
|
return MmioBitFieldRead8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -547,7 +600,8 @@ PciExpressBitFieldRead8 (
|
|||||||
Range 0..7.
|
Range 0..7.
|
||||||
@param Value The new value of the bit field.
|
@param Value The new value of the bit field.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -559,6 +613,9 @@ PciExpressBitFieldWrite8 (
|
|||||||
IN UINT8 Value
|
IN UINT8 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldWrite8 (
|
return MmioBitFieldWrite8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -591,7 +648,8 @@ PciExpressBitFieldWrite8 (
|
|||||||
Range 0..7.
|
Range 0..7.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -603,6 +661,9 @@ PciExpressBitFieldOr8 (
|
|||||||
IN UINT8 OrData
|
IN UINT8 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldOr8 (
|
return MmioBitFieldOr8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -635,7 +696,8 @@ PciExpressBitFieldOr8 (
|
|||||||
Range 0..7.
|
Range 0..7.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -647,6 +709,9 @@ PciExpressBitFieldAnd8 (
|
|||||||
IN UINT8 AndData
|
IN UINT8 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAnd8 (
|
return MmioBitFieldAnd8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -683,7 +748,8 @@ PciExpressBitFieldAnd8 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -696,6 +762,9 @@ PciExpressBitFieldAndThenOr8 (
|
|||||||
IN UINT8 OrData
|
IN UINT8 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAndThenOr8 (
|
return MmioBitFieldAndThenOr8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -718,7 +787,8 @@ PciExpressBitFieldAndThenOr8 (
|
|||||||
@param Address The address that encodes the PCI Bus, Device, Function and
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||||||
Register.
|
Register.
|
||||||
|
|
||||||
@return The read value from the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The read value from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -727,6 +797,9 @@ PciExpressRead16 (
|
|||||||
IN UINTN Address
|
IN UINTN Address
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioRead16 (GetPciExpressAddress (Address));
|
return MmioRead16 (GetPciExpressAddress (Address));
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -744,7 +817,8 @@ PciExpressRead16 (
|
|||||||
Register.
|
Register.
|
||||||
@param Value The value to write.
|
@param Value The value to write.
|
||||||
|
|
||||||
@return The value written to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -754,6 +828,9 @@ PciExpressWrite16 (
|
|||||||
IN UINT16 Value
|
IN UINT16 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioWrite16 (GetPciExpressAddress (Address), Value);
|
return MmioWrite16 (GetPciExpressAddress (Address), Value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -775,7 +852,8 @@ PciExpressWrite16 (
|
|||||||
Register.
|
Register.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -785,6 +863,9 @@ PciExpressOr16 (
|
|||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioOr16 (GetPciExpressAddress (Address), OrData);
|
return MmioOr16 (GetPciExpressAddress (Address), OrData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -806,7 +887,8 @@ PciExpressOr16 (
|
|||||||
Register.
|
Register.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -816,6 +898,9 @@ PciExpressAnd16 (
|
|||||||
IN UINT16 AndData
|
IN UINT16 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioAnd16 (GetPciExpressAddress (Address), AndData);
|
return MmioAnd16 (GetPciExpressAddress (Address), AndData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -839,7 +924,8 @@ PciExpressAnd16 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -850,6 +936,9 @@ PciExpressAndThenOr16 (
|
|||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioAndThenOr16 (
|
return MmioAndThenOr16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
AndData,
|
AndData,
|
||||||
@ -876,7 +965,8 @@ PciExpressAndThenOr16 (
|
|||||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||||
Range 0..15.
|
Range 0..15.
|
||||||
|
|
||||||
@return The value of the bit field read from the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value of the bit field read from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -887,6 +977,9 @@ PciExpressBitFieldRead16 (
|
|||||||
IN UINTN EndBit
|
IN UINTN EndBit
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldRead16 (
|
return MmioBitFieldRead16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -916,7 +1009,8 @@ PciExpressBitFieldRead16 (
|
|||||||
Range 0..15.
|
Range 0..15.
|
||||||
@param Value The new value of the bit field.
|
@param Value The new value of the bit field.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -928,6 +1022,9 @@ PciExpressBitFieldWrite16 (
|
|||||||
IN UINT16 Value
|
IN UINT16 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldWrite16 (
|
return MmioBitFieldWrite16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -961,7 +1058,8 @@ PciExpressBitFieldWrite16 (
|
|||||||
Range 0..15.
|
Range 0..15.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -973,6 +1071,9 @@ PciExpressBitFieldOr16 (
|
|||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldOr16 (
|
return MmioBitFieldOr16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1006,7 +1107,8 @@ PciExpressBitFieldOr16 (
|
|||||||
Range 0..15.
|
Range 0..15.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -1018,6 +1120,9 @@ PciExpressBitFieldAnd16 (
|
|||||||
IN UINT16 AndData
|
IN UINT16 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAnd16 (
|
return MmioBitFieldAnd16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1055,7 +1160,8 @@ PciExpressBitFieldAnd16 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -1068,6 +1174,9 @@ PciExpressBitFieldAndThenOr16 (
|
|||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAndThenOr16 (
|
return MmioBitFieldAndThenOr16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1090,7 +1199,8 @@ PciExpressBitFieldAndThenOr16 (
|
|||||||
@param Address The address that encodes the PCI Bus, Device, Function and
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||||||
Register.
|
Register.
|
||||||
|
|
||||||
@return The read value from the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The read value from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1099,6 +1209,9 @@ PciExpressRead32 (
|
|||||||
IN UINTN Address
|
IN UINTN Address
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioRead32 (GetPciExpressAddress (Address));
|
return MmioRead32 (GetPciExpressAddress (Address));
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1116,7 +1229,8 @@ PciExpressRead32 (
|
|||||||
Register.
|
Register.
|
||||||
@param Value The value to write.
|
@param Value The value to write.
|
||||||
|
|
||||||
@return The value written to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1126,6 +1240,9 @@ PciExpressWrite32 (
|
|||||||
IN UINT32 Value
|
IN UINT32 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioWrite32 (GetPciExpressAddress (Address), Value);
|
return MmioWrite32 (GetPciExpressAddress (Address), Value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1147,7 +1264,8 @@ PciExpressWrite32 (
|
|||||||
Register.
|
Register.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1157,6 +1275,9 @@ PciExpressOr32 (
|
|||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioOr32 (GetPciExpressAddress (Address), OrData);
|
return MmioOr32 (GetPciExpressAddress (Address), OrData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1178,7 +1299,8 @@ PciExpressOr32 (
|
|||||||
Register.
|
Register.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1188,6 +1310,9 @@ PciExpressAnd32 (
|
|||||||
IN UINT32 AndData
|
IN UINT32 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioAnd32 (GetPciExpressAddress (Address), AndData);
|
return MmioAnd32 (GetPciExpressAddress (Address), AndData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1211,7 +1336,8 @@ PciExpressAnd32 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1222,6 +1348,9 @@ PciExpressAndThenOr32 (
|
|||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioAndThenOr32 (
|
return MmioAndThenOr32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
AndData,
|
AndData,
|
||||||
@ -1248,7 +1377,8 @@ PciExpressAndThenOr32 (
|
|||||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||||
Range 0..31.
|
Range 0..31.
|
||||||
|
|
||||||
@return The value of the bit field read from the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value of the bit field read from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1259,6 +1389,9 @@ PciExpressBitFieldRead32 (
|
|||||||
IN UINTN EndBit
|
IN UINTN EndBit
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldRead32 (
|
return MmioBitFieldRead32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1288,7 +1421,8 @@ PciExpressBitFieldRead32 (
|
|||||||
Range 0..31.
|
Range 0..31.
|
||||||
@param Value The new value of the bit field.
|
@param Value The new value of the bit field.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1300,6 +1434,9 @@ PciExpressBitFieldWrite32 (
|
|||||||
IN UINT32 Value
|
IN UINT32 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldWrite32 (
|
return MmioBitFieldWrite32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1333,7 +1470,8 @@ PciExpressBitFieldWrite32 (
|
|||||||
Range 0..31.
|
Range 0..31.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1345,6 +1483,9 @@ PciExpressBitFieldOr32 (
|
|||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldOr32 (
|
return MmioBitFieldOr32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1378,7 +1519,8 @@ PciExpressBitFieldOr32 (
|
|||||||
Range 0..31.
|
Range 0..31.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1390,6 +1532,9 @@ PciExpressBitFieldAnd32 (
|
|||||||
IN UINT32 AndData
|
IN UINT32 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAnd32 (
|
return MmioBitFieldAnd32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1427,7 +1572,8 @@ PciExpressBitFieldAnd32 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1440,6 +1586,9 @@ PciExpressBitFieldAndThenOr32 (
|
|||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAndThenOr32 (
|
return MmioBitFieldAndThenOr32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1469,7 +1618,8 @@ PciExpressBitFieldAndThenOr32 (
|
|||||||
@param Size The size in bytes of the transfer.
|
@param Size The size in bytes of the transfer.
|
||||||
@param Buffer The pointer to a buffer receiving the data read.
|
@param Buffer The pointer to a buffer receiving the data read.
|
||||||
|
|
||||||
@return Size read data from StartAddress.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other Size read data from StartAddress.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINTN
|
UINTN
|
||||||
@ -1485,9 +1635,16 @@ PciExpressReadBuffer (
|
|||||||
//
|
//
|
||||||
// Make sure Address is valid
|
// Make sure Address is valid
|
||||||
//
|
//
|
||||||
ASSERT (((StartAddress) & ~0xfffffff) == 0);
|
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
||||||
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Make sure the Address is in MMCONF address space
|
||||||
|
//
|
||||||
|
if (StartAddress >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINTN) -1;
|
||||||
|
}
|
||||||
|
|
||||||
if (Size == 0) {
|
if (Size == 0) {
|
||||||
return Size;
|
return Size;
|
||||||
}
|
}
|
||||||
@ -1572,7 +1729,8 @@ PciExpressReadBuffer (
|
|||||||
@param Size The size in bytes of the transfer.
|
@param Size The size in bytes of the transfer.
|
||||||
@param Buffer The pointer to a buffer containing the data to write.
|
@param Buffer The pointer to a buffer containing the data to write.
|
||||||
|
|
||||||
@return Size written to StartAddress.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other Size written to StartAddress.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINTN
|
UINTN
|
||||||
@ -1588,9 +1746,16 @@ PciExpressWriteBuffer (
|
|||||||
//
|
//
|
||||||
// Make sure Address is valid
|
// Make sure Address is valid
|
||||||
//
|
//
|
||||||
ASSERT (((StartAddress) & ~0xfffffff) == 0);
|
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
||||||
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Make sure the Address is in MMCONF address space
|
||||||
|
//
|
||||||
|
if (StartAddress >= mDxeRuntimePciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINTN) -1;
|
||||||
|
}
|
||||||
|
|
||||||
if (Size == 0) {
|
if (Size == 0) {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
@ -20,9 +20,10 @@
|
|||||||
#include <Library/PcdLib.h>
|
#include <Library/PcdLib.h>
|
||||||
|
|
||||||
///
|
///
|
||||||
/// Module global that contains the base physical address of the PCI Express MMIO range.
|
/// Module global that contains the base physical address and size of the PCI Express MMIO range.
|
||||||
///
|
///
|
||||||
UINTN mSmmPciExpressLibPciExpressBaseAddress = 0;
|
UINTN mSmmPciExpressLibPciExpressBaseAddress = 0;
|
||||||
|
UINTN mSmmPciExpressLibPciExpressBaseSize = 0;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
The constructor function caches the PCI Express Base Address
|
The constructor function caches the PCI Express Base Address
|
||||||
@ -40,9 +41,10 @@ SmmPciExpressLibConstructor (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
//
|
//
|
||||||
// Cache the physical address of the PCI Express MMIO range into a module global variable
|
// Cache the physical address and size of the PCI Express MMIO range into a module global variable
|
||||||
//
|
//
|
||||||
mSmmPciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
|
mSmmPciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
|
||||||
|
mSmmPciExpressLibPciExpressBaseSize = (UINTN) PcdGet64 (PcdPciExpressBaseSize);
|
||||||
|
|
||||||
return EFI_SUCCESS;
|
return EFI_SUCCESS;
|
||||||
}
|
}
|
||||||
@ -97,8 +99,12 @@ PciExpressRegisterForRuntimeAccess (
|
|||||||
mSmmPciExpressLibPciExpressBaseAddress is initialized in the library constructor from PCD entry
|
mSmmPciExpressLibPciExpressBaseAddress is initialized in the library constructor from PCD entry
|
||||||
PcdPciExpressBaseAddress.
|
PcdPciExpressBaseAddress.
|
||||||
|
|
||||||
|
If Address > 0x0FFFFFFF, then ASSERT().
|
||||||
|
|
||||||
@param Address The address that encodes the PCI Bus, Device, Function and Register.
|
@param Address The address that encodes the PCI Bus, Device, Function and Register.
|
||||||
@return MMIO address corresponding to Address.
|
|
||||||
|
@retval (UINTN)-1 Invalid PCI address.
|
||||||
|
@retval other MMIO address corresponding to Address.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINTN
|
UINTN
|
||||||
@ -110,6 +116,12 @@ GetPciExpressAddress (
|
|||||||
// Make sure Address is valid
|
// Make sure Address is valid
|
||||||
//
|
//
|
||||||
ASSERT_INVALID_PCI_ADDRESS (Address);
|
ASSERT_INVALID_PCI_ADDRESS (Address);
|
||||||
|
//
|
||||||
|
// Make sure the Address is in MMCONF address space
|
||||||
|
//
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINTN) -1;
|
||||||
|
}
|
||||||
return mSmmPciExpressLibPciExpressBaseAddress + Address;
|
return mSmmPciExpressLibPciExpressBaseAddress + Address;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -125,7 +137,8 @@ GetPciExpressAddress (
|
|||||||
@param Address The address that encodes the PCI Bus, Device, Function and
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||||||
Register.
|
Register.
|
||||||
|
|
||||||
@return The read value from the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The read value from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -134,6 +147,9 @@ PciExpressRead8 (
|
|||||||
IN UINTN Address
|
IN UINTN Address
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioRead8 (GetPciExpressAddress (Address));
|
return MmioRead8 (GetPciExpressAddress (Address));
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -150,7 +166,8 @@ PciExpressRead8 (
|
|||||||
Register.
|
Register.
|
||||||
@param Value The value to write.
|
@param Value The value to write.
|
||||||
|
|
||||||
@return The value written to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -160,6 +177,9 @@ PciExpressWrite8 (
|
|||||||
IN UINT8 Value
|
IN UINT8 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioWrite8 (GetPciExpressAddress (Address), Value);
|
return MmioWrite8 (GetPciExpressAddress (Address), Value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -180,7 +200,8 @@ PciExpressWrite8 (
|
|||||||
Register.
|
Register.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -190,6 +211,9 @@ PciExpressOr8 (
|
|||||||
IN UINT8 OrData
|
IN UINT8 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioOr8 (GetPciExpressAddress (Address), OrData);
|
return MmioOr8 (GetPciExpressAddress (Address), OrData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -210,7 +234,8 @@ PciExpressOr8 (
|
|||||||
Register.
|
Register.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -220,6 +245,9 @@ PciExpressAnd8 (
|
|||||||
IN UINT8 AndData
|
IN UINT8 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioAnd8 (GetPciExpressAddress (Address), AndData);
|
return MmioAnd8 (GetPciExpressAddress (Address), AndData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -242,7 +270,8 @@ PciExpressAnd8 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -253,6 +282,9 @@ PciExpressAndThenOr8 (
|
|||||||
IN UINT8 OrData
|
IN UINT8 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioAndThenOr8 (
|
return MmioAndThenOr8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
AndData,
|
AndData,
|
||||||
@ -278,7 +310,8 @@ PciExpressAndThenOr8 (
|
|||||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||||
Range 0..7.
|
Range 0..7.
|
||||||
|
|
||||||
@return The value of the bit field read from the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value of the bit field read from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -289,6 +322,9 @@ PciExpressBitFieldRead8 (
|
|||||||
IN UINTN EndBit
|
IN UINTN EndBit
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldRead8 (
|
return MmioBitFieldRead8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -317,7 +353,8 @@ PciExpressBitFieldRead8 (
|
|||||||
Range 0..7.
|
Range 0..7.
|
||||||
@param Value The new value of the bit field.
|
@param Value The new value of the bit field.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -329,6 +366,9 @@ PciExpressBitFieldWrite8 (
|
|||||||
IN UINT8 Value
|
IN UINT8 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldWrite8 (
|
return MmioBitFieldWrite8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -361,7 +401,8 @@ PciExpressBitFieldWrite8 (
|
|||||||
Range 0..7.
|
Range 0..7.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -373,6 +414,9 @@ PciExpressBitFieldOr8 (
|
|||||||
IN UINT8 OrData
|
IN UINT8 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldOr8 (
|
return MmioBitFieldOr8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -405,7 +449,8 @@ PciExpressBitFieldOr8 (
|
|||||||
Range 0..7.
|
Range 0..7.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -417,6 +462,9 @@ PciExpressBitFieldAnd8 (
|
|||||||
IN UINT8 AndData
|
IN UINT8 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAnd8 (
|
return MmioBitFieldAnd8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -453,7 +501,8 @@ PciExpressBitFieldAnd8 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT8
|
UINT8
|
||||||
@ -466,6 +515,9 @@ PciExpressBitFieldAndThenOr8 (
|
|||||||
IN UINT8 OrData
|
IN UINT8 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT8) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAndThenOr8 (
|
return MmioBitFieldAndThenOr8 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -488,7 +540,8 @@ PciExpressBitFieldAndThenOr8 (
|
|||||||
@param Address The address that encodes the PCI Bus, Device, Function and
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||||||
Register.
|
Register.
|
||||||
|
|
||||||
@return The read value from the PCI configuration register.
|
@retval 0xFF Invalid PCI address.
|
||||||
|
@retval other The read value from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -497,6 +550,9 @@ PciExpressRead16 (
|
|||||||
IN UINTN Address
|
IN UINTN Address
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioRead16 (GetPciExpressAddress (Address));
|
return MmioRead16 (GetPciExpressAddress (Address));
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -514,7 +570,8 @@ PciExpressRead16 (
|
|||||||
Register.
|
Register.
|
||||||
@param Value The value to write.
|
@param Value The value to write.
|
||||||
|
|
||||||
@return The value written to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -524,6 +581,9 @@ PciExpressWrite16 (
|
|||||||
IN UINT16 Value
|
IN UINT16 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioWrite16 (GetPciExpressAddress (Address), Value);
|
return MmioWrite16 (GetPciExpressAddress (Address), Value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -545,7 +605,8 @@ PciExpressWrite16 (
|
|||||||
Register.
|
Register.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -555,6 +616,9 @@ PciExpressOr16 (
|
|||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioOr16 (GetPciExpressAddress (Address), OrData);
|
return MmioOr16 (GetPciExpressAddress (Address), OrData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -576,7 +640,8 @@ PciExpressOr16 (
|
|||||||
Register.
|
Register.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -586,6 +651,9 @@ PciExpressAnd16 (
|
|||||||
IN UINT16 AndData
|
IN UINT16 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioAnd16 (GetPciExpressAddress (Address), AndData);
|
return MmioAnd16 (GetPciExpressAddress (Address), AndData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -609,7 +677,8 @@ PciExpressAnd16 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -620,6 +689,9 @@ PciExpressAndThenOr16 (
|
|||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioAndThenOr16 (
|
return MmioAndThenOr16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
AndData,
|
AndData,
|
||||||
@ -646,7 +718,8 @@ PciExpressAndThenOr16 (
|
|||||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||||
Range 0..15.
|
Range 0..15.
|
||||||
|
|
||||||
@return The value of the bit field read from the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value of the bit field read from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -657,6 +730,9 @@ PciExpressBitFieldRead16 (
|
|||||||
IN UINTN EndBit
|
IN UINTN EndBit
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldRead16 (
|
return MmioBitFieldRead16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -686,7 +762,8 @@ PciExpressBitFieldRead16 (
|
|||||||
Range 0..15.
|
Range 0..15.
|
||||||
@param Value The new value of the bit field.
|
@param Value The new value of the bit field.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -698,6 +775,9 @@ PciExpressBitFieldWrite16 (
|
|||||||
IN UINT16 Value
|
IN UINT16 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldWrite16 (
|
return MmioBitFieldWrite16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -731,7 +811,8 @@ PciExpressBitFieldWrite16 (
|
|||||||
Range 0..15.
|
Range 0..15.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -743,6 +824,9 @@ PciExpressBitFieldOr16 (
|
|||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldOr16 (
|
return MmioBitFieldOr16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -776,7 +860,8 @@ PciExpressBitFieldOr16 (
|
|||||||
Range 0..15.
|
Range 0..15.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -788,6 +873,9 @@ PciExpressBitFieldAnd16 (
|
|||||||
IN UINT16 AndData
|
IN UINT16 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAnd16 (
|
return MmioBitFieldAnd16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -825,7 +913,8 @@ PciExpressBitFieldAnd16 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT16
|
UINT16
|
||||||
@ -838,6 +927,9 @@ PciExpressBitFieldAndThenOr16 (
|
|||||||
IN UINT16 OrData
|
IN UINT16 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT16) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAndThenOr16 (
|
return MmioBitFieldAndThenOr16 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -860,7 +952,8 @@ PciExpressBitFieldAndThenOr16 (
|
|||||||
@param Address The address that encodes the PCI Bus, Device, Function and
|
@param Address The address that encodes the PCI Bus, Device, Function and
|
||||||
Register.
|
Register.
|
||||||
|
|
||||||
@return The read value from the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The read value from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -869,6 +962,9 @@ PciExpressRead32 (
|
|||||||
IN UINTN Address
|
IN UINTN Address
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioRead32 (GetPciExpressAddress (Address));
|
return MmioRead32 (GetPciExpressAddress (Address));
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -886,7 +982,8 @@ PciExpressRead32 (
|
|||||||
Register.
|
Register.
|
||||||
@param Value The value to write.
|
@param Value The value to write.
|
||||||
|
|
||||||
@return The value written to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -896,6 +993,9 @@ PciExpressWrite32 (
|
|||||||
IN UINT32 Value
|
IN UINT32 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioWrite32 (GetPciExpressAddress (Address), Value);
|
return MmioWrite32 (GetPciExpressAddress (Address), Value);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -917,7 +1017,8 @@ PciExpressWrite32 (
|
|||||||
Register.
|
Register.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -927,6 +1028,9 @@ PciExpressOr32 (
|
|||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioOr32 (GetPciExpressAddress (Address), OrData);
|
return MmioOr32 (GetPciExpressAddress (Address), OrData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -948,7 +1052,8 @@ PciExpressOr32 (
|
|||||||
Register.
|
Register.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -958,6 +1063,9 @@ PciExpressAnd32 (
|
|||||||
IN UINT32 AndData
|
IN UINT32 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioAnd32 (GetPciExpressAddress (Address), AndData);
|
return MmioAnd32 (GetPciExpressAddress (Address), AndData);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -981,7 +1089,8 @@ PciExpressAnd32 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -992,6 +1101,9 @@ PciExpressAndThenOr32 (
|
|||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioAndThenOr32 (
|
return MmioAndThenOr32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
AndData,
|
AndData,
|
||||||
@ -1018,7 +1130,8 @@ PciExpressAndThenOr32 (
|
|||||||
@param EndBit The ordinal of the most significant bit in the bit field.
|
@param EndBit The ordinal of the most significant bit in the bit field.
|
||||||
Range 0..31.
|
Range 0..31.
|
||||||
|
|
||||||
@return The value of the bit field read from the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value of the bit field read from the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1029,6 +1142,9 @@ PciExpressBitFieldRead32 (
|
|||||||
IN UINTN EndBit
|
IN UINTN EndBit
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldRead32 (
|
return MmioBitFieldRead32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1058,7 +1174,8 @@ PciExpressBitFieldRead32 (
|
|||||||
Range 0..31.
|
Range 0..31.
|
||||||
@param Value The new value of the bit field.
|
@param Value The new value of the bit field.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1070,6 +1187,9 @@ PciExpressBitFieldWrite32 (
|
|||||||
IN UINT32 Value
|
IN UINT32 Value
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldWrite32 (
|
return MmioBitFieldWrite32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1103,7 +1223,8 @@ PciExpressBitFieldWrite32 (
|
|||||||
Range 0..31.
|
Range 0..31.
|
||||||
@param OrData The value to OR with the PCI configuration register.
|
@param OrData The value to OR with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1115,6 +1236,9 @@ PciExpressBitFieldOr32 (
|
|||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldOr32 (
|
return MmioBitFieldOr32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1148,7 +1272,8 @@ PciExpressBitFieldOr32 (
|
|||||||
Range 0..31.
|
Range 0..31.
|
||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1160,6 +1285,9 @@ PciExpressBitFieldAnd32 (
|
|||||||
IN UINT32 AndData
|
IN UINT32 AndData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAnd32 (
|
return MmioBitFieldAnd32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1197,7 +1325,8 @@ PciExpressBitFieldAnd32 (
|
|||||||
@param AndData The value to AND with the PCI configuration register.
|
@param AndData The value to AND with the PCI configuration register.
|
||||||
@param OrData The value to OR with the result of the AND operation.
|
@param OrData The value to OR with the result of the AND operation.
|
||||||
|
|
||||||
@return The value written back to the PCI configuration register.
|
@retval 0xFFFFFFFF Invalid PCI address.
|
||||||
|
@retval other The value written back to the PCI configuration register.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINT32
|
UINT32
|
||||||
@ -1210,6 +1339,9 @@ PciExpressBitFieldAndThenOr32 (
|
|||||||
IN UINT32 OrData
|
IN UINT32 OrData
|
||||||
)
|
)
|
||||||
{
|
{
|
||||||
|
if (Address >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINT32) -1;
|
||||||
|
}
|
||||||
return MmioBitFieldAndThenOr32 (
|
return MmioBitFieldAndThenOr32 (
|
||||||
GetPciExpressAddress (Address),
|
GetPciExpressAddress (Address),
|
||||||
StartBit,
|
StartBit,
|
||||||
@ -1239,7 +1371,8 @@ PciExpressBitFieldAndThenOr32 (
|
|||||||
@param Size The size in bytes of the transfer.
|
@param Size The size in bytes of the transfer.
|
||||||
@param Buffer The pointer to a buffer receiving the data read.
|
@param Buffer The pointer to a buffer receiving the data read.
|
||||||
|
|
||||||
@return Size read data from StartAddress.
|
@retval (UINTN)-1 Invalid PCI address.
|
||||||
|
@retval other Size read data from StartAddress.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINTN
|
UINTN
|
||||||
@ -1258,6 +1391,13 @@ PciExpressReadBuffer (
|
|||||||
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
||||||
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Make sure the Address is in MMCONF address space
|
||||||
|
//
|
||||||
|
if (StartAddress >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINTN) -1;
|
||||||
|
}
|
||||||
|
|
||||||
if (Size == 0) {
|
if (Size == 0) {
|
||||||
return Size;
|
return Size;
|
||||||
}
|
}
|
||||||
@ -1342,7 +1482,8 @@ PciExpressReadBuffer (
|
|||||||
@param Size The size in bytes of the transfer.
|
@param Size The size in bytes of the transfer.
|
||||||
@param Buffer The pointer to a buffer containing the data to write.
|
@param Buffer The pointer to a buffer containing the data to write.
|
||||||
|
|
||||||
@return Size written to StartAddress.
|
@retval (UINTN)-1 Invalid PCI address.
|
||||||
|
@retval other Size written to StartAddress.
|
||||||
|
|
||||||
**/
|
**/
|
||||||
UINTN
|
UINTN
|
||||||
@ -1361,6 +1502,13 @@ PciExpressWriteBuffer (
|
|||||||
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
|
||||||
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Make sure the Address is in MMCONF address space
|
||||||
|
//
|
||||||
|
if (StartAddress >= mSmmPciExpressLibPciExpressBaseSize) {
|
||||||
|
return (UINTN) -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
if (Size == 0) {
|
if (Size == 0) {
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -35,3 +35,4 @@
|
|||||||
|
|
||||||
[Pcd]
|
[Pcd]
|
||||||
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
|
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
|
||||||
|
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize ## CONSUMES
|
||||||
|
@ -2274,6 +2274,10 @@
|
|||||||
# @Prompt PCI Express Base Address.
|
# @Prompt PCI Express Base Address.
|
||||||
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x0000000a
|
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000|UINT64|0x0000000a
|
||||||
|
|
||||||
|
## This value is used to set the size of PCI express hierarchy. The default is 256 MB.
|
||||||
|
# @Prompt PCI Express Base Size.
|
||||||
|
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000|UINT64|0x0000000f
|
||||||
|
|
||||||
## Default current ISO 639-2 language: English & French.
|
## Default current ISO 639-2 language: English & French.
|
||||||
# @Prompt Default Value of LangCodes Variable.
|
# @Prompt Default Value of LangCodes Variable.
|
||||||
gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|VOID*|0x0000001c
|
gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultLangCodes|"engfraengfra"|VOID*|0x0000001c
|
||||||
|
Loading…
x
Reference in New Issue
Block a user