mirror of https://github.com/acidanthera/audk.git
IntelSiliconPkg: Fixed VBT size bug, typos and updated comments
1) Fixed the VBT size from 0x1C00(7KB) to 0x1800(6KB) and typos, indentation 2) Updated offsets in hex values and offset from start of OPREGION Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Mudusuru, Giri P
Jiewen Yao
parent
a61331e8b7
commit
5c66efd0ed
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@ -9,7 +9,7 @@
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1) INTEL_IGD_OPREGION_HEADER.RSV1[0xA0]
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2) INTEL_IGD_OPREGION_MBOX1.RSV3[0x3C]
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3) INTEL_IGD_OPREGION_MBOX3.RSV5[0x62]
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4) INTEL_IGD_OPREGION_VBT.RVBT[0x1C00]
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4) INTEL_IGD_OPREGION_VBT.RVBT[0x1800] Size is 6KB
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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@ -25,101 +25,102 @@
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#define _IGD_OPREGION_H_
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/**
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OpRegion structures:
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Sub-structures define the different parts of the OpRegion followed by the
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main structure representing the entire OpRegion.
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OpRegion structures:
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Sub-structures define the different parts of the OpRegion followed by the
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main structure representing the entire OpRegion.
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Note: These structures are packed to 1 byte offsets because the exact
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data location is requred by the supporting design specification due to
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the fact that the data is used by ASL and Graphics driver code compiled
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separatly.
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@note: These structures are packed to 1 byte offsets because the exact
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data location is required by the supporting design specification due to
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the fact that the data is used by ASL and Graphics driver code compiled
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separately.
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**/
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#pragma pack(1)
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///
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/// OpRegion header (mailbox 0) structure and defines.
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/// OpRegion header (mailbox 0) structure. The OpRegion Header is used to
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/// identify a block of memory as the graphics driver OpRegion.
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///
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typedef struct {
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CHAR8 SIGN[0x10]; ///< Offset 0 OpRegion Signature
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UINT32 SIZE; ///< Offset 16 OpRegion Size
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UINT32 OVER; ///< Offset 20 OpRegion Structure Version
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UINT8 SVER[0x20]; ///< Offset 24 System BIOS Build Version
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UINT8 VVER[0x10]; ///< Offset 56 Video BIOS Build Version
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UINT8 GVER[0x10]; ///< Offset 72 Graphic Driver Build Version
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UINT32 MBOX; ///< Offset 88 Supported Mailboxes
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UINT32 DMOD; ///< Offset 92 Driver Model
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UINT8 RSV1[0xA0]; ///< Offset 96 Reserved
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CHAR8 SIGN[0x10]; ///< Offset 0x00 OpRegion Signature
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UINT32 SIZE; ///< Offset 0x10 OpRegion Size
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UINT32 OVER; ///< Offset 0x14 OpRegion Structure Version
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UINT8 SVER[0x20]; ///< Offset 0x18 System BIOS Build Version
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UINT8 VVER[0x10]; ///< Offset 0x38 Video BIOS Build Version
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UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version
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UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes
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UINT32 DMOD; ///< Offset 0x5C Driver Model
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UINT8 RSV1[0xA0]; ///< Offset 0x60 Reserved
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} INTEL_IGD_OPREGION_HEADER;
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///
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/// OpRegion mailbox 1 (public ACPI Methods).
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/// OpRegion mailbox 1 (public ACPI Methods)
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///
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typedef struct {
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UINT32 DRDY; ///< Offset 0 Driver Readiness
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UINT32 CSTS; ///< Offset 4 Status
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UINT32 CEVT; ///< Offset 8 Current Event
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UINT8 RSV2[0x14]; ///< Offset 12 Reserved
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UINT32 DIDL[8]; ///< Offset 32 Supported Display Devices ID List
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UINT32 CPDL[8]; ///< Offset 64 Currently Attached Display Devices List
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UINT32 CADL[8]; ///< Offset 96 Currently Active Display Devices List
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UINT32 NADL[8]; ///< Offset 128 Next Active Devices List
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UINT32 ASLP; ///< Offset 160 ASL Sleep Time Out
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UINT32 TIDX; ///< Offset 164 Toggle Table Index
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UINT32 CHPD; ///< Offset 168 Current Hotplug Enable Indicator
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UINT32 CLID; ///< Offset 172 Current Lid State Indicator
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UINT32 CDCK; ///< Offset 176 Current Docking State Indicator
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UINT32 SXSW; ///< Offset 180 Display Switch Notification on Sx State Resume
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UINT32 EVTS; ///< Offset 184 Events supported by ASL
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UINT32 CNOT; ///< Offset 188 Current OS Notification
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UINT32 NRDY; ///< Offset 192 Driver Status
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UINT8 RSV3[0x3C]; ///< Offset 196 Reserved
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UINT32 DRDY; ///< Offset 0x100 Driver Readiness
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UINT32 CSTS; ///< Offset 0x104 Status
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UINT32 CEVT; ///< Offset 0x108 Current Event
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UINT8 RSV2[0x14]; ///< Offset 0x10C Reserved
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UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List
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UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devices List
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UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices List
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UINT32 NADL[8]; ///< Offset 0x180 Next Active Devices List
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UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out
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UINT32 TIDX; ///< Offset 0x1A4 Toggle Table Index
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UINT32 CHPD; ///< Offset 0x1A8 Current Hotplug Enable Indicator
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UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator
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UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator
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UINT32 SXSW; ///< Offset 0x1B4 Display Switch Notification on Sx State Resume
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UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL
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UINT32 CNOT; ///< Offset 0x1BC Current OS Notification
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UINT32 NRDY; ///< Offset 0x1C0 Driver Status
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UINT8 RSV3[0x3C]; ///< Offset 0x1C4 - 0x1FF Reserved
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} INTEL_IGD_OPREGION_MBOX1;
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///
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/// OpRegion mailbox 2 (Software SCI Interface).
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///
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typedef struct {
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UINT32 SCIC; ///< Offset 0 Software SCI Command / Status / Data
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UINT32 PARM; ///< Offset 4 Software SCI Parameters
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UINT32 DSLP; ///< Offset 8 Driver Sleep Time Out
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UINT8 RSV4[0xF4]; ///< Offset 12 Reserved
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UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / Data
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UINT32 PARM; ///< Offset 0x204 Software SCI Parameters
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UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out
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UINT8 RSV4[0xF4]; ///< Offset 0x20C - 0x2FF Reserved
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} INTEL_IGD_OPREGION_MBOX2;
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///
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/// OpRegion mailbox 3 (BIOS/Driver Communication - ASLE Support).
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///
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typedef struct {
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UINT32 ARDY; ///< Offset 0 Driver Readiness
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UINT32 ASLC; ///< Offset 4 ASLE Interrupt Command / Status
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UINT32 TCHE; ///< Offset 8 Technology Enabled Indicator
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UINT32 ALSI; ///< Offset 12 Current ALS Luminance Reading
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UINT32 BCLP; ///< Offset 16 Requested Backlight Britness
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UINT32 PFIT; ///< Offset 20 Panel Fitting State or Request
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UINT32 CBLV; ///< Offset 24 Current Brightness Level
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UINT16 BCLM[0x14]; ///< Offset 28 Backlight Brightness Levels Duty Cycle Mapping Table
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UINT32 CPFM; ///< Offset 68 Current Panel Fitting Mode
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UINT32 EPFM; ///< Offset 72 Enabled Panel Fitting Modes
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UINT8 PLUT[0x4A]; ///< Offset 76 Panel Look Up Table & Identifier
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UINT32 PFMB; ///< Offset 150 PWM Frequency and Minimum Brightness
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UINT32 CCDV; ///< Offset 154 Color Correction Default Values
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UINT8 RSV5[0x62]; ///< Offset 158 Reserved
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UINT32 ARDY; ///< Offset 0x300 Driver Readiness
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UINT32 ASLC; ///< Offset 0x304 ASLE Interrupt Command / Status
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UINT32 TCHE; ///< Offset 0x308 Technology Enabled Indicator
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UINT32 ALSI; ///< Offset 0x30C Current ALS Luminance Reading
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UINT32 BCLP; ///< Offset 0x310 Requested Backlight Brightness
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UINT32 PFIT; ///< Offset 0x314 Panel Fitting State or Request
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UINT32 CBLV; ///< Offset 0x318 Current Brightness Level
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UINT16 BCLM[0x14]; ///< Offset 0x31C Backlight Brightness Levels Duty Cycle Mapping Table
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UINT32 CPFM; ///< Offset 0x344 Current Panel Fitting Mode
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UINT32 EPFM; ///< Offset 0x348 Enabled Panel Fitting Modes
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UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier
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UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Brightness
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UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values
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UINT8 RSV5[0x62]; ///< Offset 0x39E - 0x3FF Reserved
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} INTEL_IGD_OPREGION_MBOX3;
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///
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/// OpRegion mailbox 4 (VBT).
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///
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typedef struct {
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UINT8 RVBT[0x1C00]; ///< Offset 0 Raw VBT Data
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UINT8 RVBT[0x1800]; ///< Offset 0x400 - 0x1BFF Raw VBT Data
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} INTEL_IGD_OPREGION_VBT;
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///
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/// IGD OpRegion Structure
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///
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typedef struct {
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INTEL_IGD_OPREGION_HEADER Header; ///< OpRegion header
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INTEL_IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods
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INTEL_IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Inteface
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INTEL_IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS/Driver Communication
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INTEL_IGD_OPREGION_VBT VBT; ///< VBT: Video BIOS Table (OEM customizable data)
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INTEL_IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100)
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INTEL_IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods (Offset 0x100, Size 0x100)
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INTEL_IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offset 0x200, Size 0x100)
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INTEL_IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Communication (Offset 0x300, Size 0x100)
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INTEL_IGD_OPREGION_VBT VBT; ///< Mailbox 4: Video BIOS Table (VBT) (Offset 0x400, Size 0x1200)
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} IGD_IGD_OPREGION_STRUCTURE;
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#pragma pack()
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