mirror of https://github.com/acidanthera/audk.git
Add dual FSP binaries support.
There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version) TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17249 6f19259b-4bc3-4df7-8a09-765794883524
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@ -81,6 +81,7 @@
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[Pcd]
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gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES
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gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase ## CONSUMES
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gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase ## CONSUMES
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gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize ## CONSUMES
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gFspWrapperTokenSpaceGuid.PcdMaxUpdRegionSize ## CONSUMES
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gFspWrapperTokenSpaceGuid.PcdFspApiVersion ## CONSUMES
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@ -261,7 +261,11 @@ PeiMemoryDiscoveredNotify (
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VOID *FspHobList;
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EFI_HOB_GUID_TYPE *GuidHob;
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FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
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if (PcdGet32 (PcdFlashFvSecondFspBase) == 0) {
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FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
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} else {
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FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvSecondFspBase));
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}
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if (FspHeader == NULL) {
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return EFI_DEVICE_ERROR;
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}
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@ -120,7 +120,11 @@ FspDxeEntryPoint (
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VOID *Registration;
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EFI_EVENT ProtocolNotifyEvent;
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mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
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if (PcdGet32 (PcdFlashFvSecondFspBase) == 0) {
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mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));
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} else {
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mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvSecondFspBase));
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}
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DEBUG ((DEBUG_INFO, "FspHeader - 0x%x\n", mFspHeader));
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if (mFspHeader == NULL) {
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return EFI_DEVICE_ERROR;
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@ -49,6 +49,7 @@
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[Pcd]
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gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase ## CONSUMES
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gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase ## CONSUMES
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gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize ## CONSUMES
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[Depex]
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@ -59,10 +59,22 @@
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## Provides the size of the BIOS Flash Device.
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gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002
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## Indicates the base address of the FSP binary.
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## Indicates the base address of the factory FSP binary.
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gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000|UINT32|0x10000003
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## Provides the size of the FSP binary.
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## Indicates the base address of the updatable FSP binary to support Dual FSP.
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# There could be two FSP images at different locations in a flash -
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# one factory version (default) and updatable version (updatable).
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# TempRamInit, FspMemoryInit and TempRamExit are always executed from factory version.
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# FspSiliconInit and NotifyPhase can be executed from updatable version if it is available,
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# FspSiliconInit and NotifyPhase are executed from factory version if there is no updateable version,
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# PcdFlashFvFspBase is base address of factory FSP, and PcdFlashFvSecondFspBase
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# is base address of updatable FSP. If PcdFlashFvSecondFspBase is 0, that means
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# there is no updatable FSP.
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gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase|0x00000000|UINT32|0x10000008
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## Provides the size of the factory FSP binary.
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gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000|UINT32|0x10000004
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## Provides the size of the updatable FSP binary to support Dual FSP.
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gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspSize|0x00000000|UINT32|0x10000009
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## Indicates the base address of the first Microcode Patch in the Microcode Region
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gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005
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