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MdeModulePkg/NvmExpressDxe: comments update to meet implementation 

Cc: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com>
Cc: Wu, Hao A <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Wu, Hao A <hao.a.wu@intel.com>
Reviewed-by: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com>
This commit is contained in:
Feng Tian 2016-04-26 14:49:53 +08:00
parent 6a0d242212
commit 5db1ac89be
1 changed files with 5 additions and 7 deletions
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12
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.h
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@ -2,7 +2,7 @@
NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
NVM Express specification. NVM Express specification.
Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR> Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -101,13 +101,11 @@ struct _NVME_CONTROLLER_PRIVATE_DATA {
NVME_ADMIN_CONTROLLER_DATA *ControllerData; NVME_ADMIN_CONTROLLER_DATA *ControllerData;
// //
// 6 x 4kB aligned buffers will be carved out of this buffer. // 4 x 4kB aligned buffers will be carved out of this buffer.
// 1st 4kB boundary is the start of the admin submission queue. // 1st 4kB boundary is the start of the admin submission queue.
// 2nd 4kB boundary is the start of the I/O submission queue #1. // 2nd 4kB boundary is the start of the admin completion queue.
// 3rd 4kB boundary is the start of the admin completion queue. // 3rd 4kB boundary is the start of I/O submission queue #1.
// 4th 4kB boundary is the start of the I/O completion queue #1. // 4th 4kB boundary is the start of I/O completion queue #1.
// 5th 4kB boundary is the start of the first PRP list page.
// 6th 4kB boundary is the start of the second PRP list page.
// //
UINT8 *Buffer; UINT8 *Buffer;
UINT8 *BufferPciAddr; UINT8 *BufferPciAddr;