mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/NvmExpressDxe: comments update to meet implementation
Cc: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com> Cc: Wu, Hao A <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Wu, Hao A <hao.a.wu@intel.com> Reviewed-by: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com>
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@ -2,7 +2,7 @@
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NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows
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NVM Express specification.
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Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -101,13 +101,11 @@ struct _NVME_CONTROLLER_PRIVATE_DATA {
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NVME_ADMIN_CONTROLLER_DATA *ControllerData;
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//
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// 6 x 4kB aligned buffers will be carved out of this buffer.
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// 4 x 4kB aligned buffers will be carved out of this buffer.
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// 1st 4kB boundary is the start of the admin submission queue.
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// 2nd 4kB boundary is the start of the I/O submission queue #1.
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// 3rd 4kB boundary is the start of the admin completion queue.
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// 4th 4kB boundary is the start of the I/O completion queue #1.
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// 5th 4kB boundary is the start of the first PRP list page.
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// 6th 4kB boundary is the start of the second PRP list page.
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// 2nd 4kB boundary is the start of the admin completion queue.
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// 3rd 4kB boundary is the start of I/O submission queue #1.
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// 4th 4kB boundary is the start of I/O completion queue #1.
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//
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UINT8 *Buffer;
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UINT8 *BufferPciAddr;
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