mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/PciBusDxe: Enable Bus Master on P2P bridges on demand
The patch dynamically enables Bus Master on P2P bridges only when requested by a device driver through PciIo.Attribute() to enable the Bus Master. Signed-off-by: Sean Brogan <sean.brogan@microsoft.com> Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com>
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@ -1,7 +1,7 @@
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/** @file
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Supporting functions implementaion for PCI devices management.
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Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -711,7 +711,12 @@ StartPciDevicesOnBridge (
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0,
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&Supports
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);
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Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
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//
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// By default every bridge's IO and MMIO spaces are enabled.
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// Bridge's Bus Master will be enabled when any device behind it requests
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// to enable Bus Master.
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//
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Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);
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PciIoDevice->PciIo.Attributes (
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&(PciIoDevice->PciIo),
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EfiPciIoAttributeOperationEnable,
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@ -763,7 +768,12 @@ StartPciDevicesOnBridge (
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0,
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&Supports
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);
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Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;
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//
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// By default every bridge's IO and MMIO spaces are enabled.
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// Bridge's Bus Master will be enabled when any device behind it requests
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// to enable Bus Master.
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//
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Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);
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PciIoDevice->PciIo.Attributes (
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&(PciIoDevice->PciIo),
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EfiPciIoAttributeOperationEnable,
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@ -1218,11 +1218,12 @@ DetermineDeviceAttribute (
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return Status;
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}
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//
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// Assume the PCI Root Bridge supports DAC
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// Assume the PCI Root Bridge supports DAC and Bus Master.
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//
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PciIoDevice->Supports |= (UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
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EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
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EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
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EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE |
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EFI_PCI_IO_ATTRIBUTE_BUS_MASTER);
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} else {
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@ -1233,9 +1234,16 @@ DetermineDeviceAttribute (
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//
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Command = EFI_PCI_COMMAND_IO_SPACE |
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EFI_PCI_COMMAND_MEMORY_SPACE |
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EFI_PCI_COMMAND_BUS_MASTER |
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EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
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//
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// Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus Master capable.
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// So only test the Bus Master capability for PCI devices.
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//
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if (!IS_PCI_BRIDGE(&PciIoDevice->Pci)) {
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Command |= EFI_PCI_COMMAND_BUS_MASTER;
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}
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BridgeControl = EFI_PCI_BRIDGE_CONTROL_ISA | EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_16;
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//
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@ -1245,7 +1253,11 @@ DetermineDeviceAttribute (
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//
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// Set the supported attributes for specified PCI device
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// Per PCI-to-PCI Bridge Architecture all PCI-to-PCI bridges are Bus Master capable.
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//
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if (IS_PCI_BRIDGE(&PciIoDevice->Pci)) {
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Command |= EFI_PCI_COMMAND_BUS_MASTER;
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}
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PciSetDeviceAttribute (PciIoDevice, Command, BridgeControl, EFI_SET_SUPPORTS);
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//
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@ -1348,7 +1348,8 @@ ModifyRootBridgeAttributes (
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//
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Attributes &= ~(UINT64)(EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE |
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EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM |
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EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE);
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EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE |
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EFI_PCI_IO_ATTRIBUTE_BUS_MASTER);
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//
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// Record the new attribute of the Root Bridge
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@ -1726,12 +1727,11 @@ PciIoAttributes (
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}
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//
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// The upstream bridge should be also set to revelant attribute
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// expect for IO, Mem and BusMaster
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// expect for IO and Mem
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//
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UpStreamAttributes = Attributes &
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(~(EFI_PCI_IO_ATTRIBUTE_IO |
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EFI_PCI_IO_ATTRIBUTE_MEMORY |
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EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
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EFI_PCI_IO_ATTRIBUTE_MEMORY
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)
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);
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UpStreamBridge = PciIoDevice->Parent;
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