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ArmPlatformPkg/Sec: Allowed the Secondary Cores to set the Secure/Non Secure bits to their PPIs 

The GICD_IGROUPR0 is banked for each connected processor. It means the
Non-Secure bits for the PPIs (Private Peripheral Interrupts) must be
configured for every processor.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13135 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2012-03-26 11:03:36 +00:00
parent 18029bb911
commit 5e7731443c
12 changed files with 47 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@ -1,6 +1,6 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@ -13,6 +13,7 @@
**/
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
@ -24,6 +25,7 @@
VOID
EFIAPI
ArmGicSetupNonSecure (
IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
)
@ -47,9 +49,15 @@ ArmGicSetupNonSecure (
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
}
// Ensure all GIC interrupts are Non-Secure
for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
// Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
if (IS_PRIMARY_CORE(MpId)) {
// Ensure all GIC interrupts are Non-Secure
for (Index = 0; Index < (PcdGet32(PcdGicNumInterrupts) / 32); Index++) {
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
}
} else {
// The secondary cores only set the Non Secure bit to their banked PPIs
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
}
// Ensure all interrupts can get through the priority mask

6
ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
View File

@ -1,5 +1,5 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -28,6 +28,7 @@
MdePkg/MdePkg.dec
[LibraryClasses]
ArmLib
DebugLib
IoLib
PcdLib
@ -35,3 +36,6 @@
[FixedPcd.common]
gArmTokenSpaceGuid.PcdGicNumInterrupts
gArmTokenSpaceGuid.PcdGicSgiIntId
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

3
ArmPkg/Include/Library/ArmGicLib.h
View File

@ -1,6 +1,6 @@
/** @file
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@ -77,6 +77,7 @@
VOID
EFIAPI
ArmGicSetupNonSecure (
IN UINTN MpId,
IN INTN GicDistributorBase,
IN INTN GicInterruptInterfaceBase
);

2
ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbSec.c
View File

@ -31,7 +31,7 @@
**/
VOID
ArmPlatformTrustzoneInit (
VOID
IN UINTN MpId
)
{
ASSERT(FALSE);

3
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressSecLib.inf
View File

@ -52,3 +52,6 @@
gArmTokenSpaceGuid.PcdTrustzoneSupport
gArmTokenSpaceGuid.PcdL2x0ControllerBase
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

7
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4Sec.c
View File

@ -32,9 +32,14 @@
**/
VOID
ArmPlatformTrustzoneInit (
VOID
IN UINTN MpId
)
{
// Nothing to do
if (!IS_PRIMARY_CORE(MpId)) {
return;
}
//
// Setup TZ Protection Controller
//

2
ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMSec.c
View File

@ -31,7 +31,7 @@
**/
VOID
ArmPlatformTrustzoneInit (
VOID
IN UINTN MpId
)
{
// No TZPC or TZASC on RTSM to initialize

2
ArmPlatformPkg/Include/Library/ArmPlatformLib.h
View File

@ -140,7 +140,7 @@ ArmPlatformInitializeSystemMemory (
**/
VOID
ArmPlatformTrustzoneInit (
VOID
IN UINTN MpId
);
/**

7
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullSec.c
View File

@ -25,9 +25,14 @@
**/
VOID
ArmPlatformTrustzoneInit (
VOID
IN UINTN MpId
)
{
// Secondary cores might have to set the Secure SGIs into the GICD_IGROUPR0
if (!IS_PRIMARY_CORE(MpId)) {
return;
}
ASSERT(FALSE);
}

5
ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNullSec.inf
View File

@ -1,5 +1,5 @@
#/* @file
# Copyright (c) 2011, ARM Limited. All rights reserved.
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -37,3 +37,6 @@
[FixedPcd]
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
gArmTokenSpaceGuid.PcdArmPrimaryCore

12
ArmPlatformPkg/Sec/Sec.c
View File

@ -144,14 +144,14 @@ TrustedWorldInitialization (
// Set up Monitor World (Vector Table, etc)
ArmSecureMonitorWorldInitialize ();
// Transfer the interrupt to Non-secure World
ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
// Initialize platform specific security policy
ArmPlatformTrustzoneInit (MpId);
// Setup the Trustzone Chipsets
if (IS_PRIMARY_CORE(MpId)) {
// Transfer the interrupt to Non-secure World
ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
// Initialize platform specific security policy
ArmPlatformTrustzoneInit ();
if (ArmIsMpCore()) {
// Waiting for the Primary Core to have finished to initialize the Secure World
ArmCpuSynchronizeSignal (ARM_CPU_EVENT_SECURE_INIT);

15
BeagleBoardPkg/Library/BeagleBoardLib/BeagleBoard.c
View File

@ -74,21 +74,6 @@ ArmPlatformTrustzoneSupported (
return FALSE;
}
/**
Initialize the Secure peripherals and memory regions
If Trustzone is supported by your platform then this function makes the required initialization
of the secure peripherals and memory regions.
**/
VOID
ArmPlatformTrustzoneInit (
VOID
)
{
ASSERT(FALSE);
}
/**
Remap the memory at 0x0