mirror of https://github.com/acidanthera/audk.git
SourceLevelDebugPkg/DebugAgent: Support IA32 processors without DE or FXSAVE/FXRESTOR
Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions. Do not enable those features in CR4 if they are not supported. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17220 6f19259b-4bc3-4df7-8a09-765794883524
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@ -1,7 +1,7 @@
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/** @file
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Supporting functions for IA32 architecture.
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Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -28,6 +28,7 @@ InitializeDebugIdt (
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IA32_DESCRIPTOR IdtDescriptor;
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UINTN Index;
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UINT16 CodeSegment;
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UINT32 RegEdx;
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AsmReadIdtr (&IdtDescriptor);
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@ -59,10 +60,14 @@ InitializeDebugIdt (
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IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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//
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// If the CPU supports Debug Extensions(CPUID:01 EDX:BIT2), then
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// Set DE flag in CR4 to enable IO breakpoint
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//
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AsmCpuid (1, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT2) != 0) {
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AsmWriteCr4 (AsmReadCr4 () | BIT3);
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}
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}
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/**
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Retrieve exception handler from IDT table by ExceptionNum.
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@ -1,6 +1,6 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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@ -232,10 +232,25 @@ NoExtrPush:
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pushl %edi
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## UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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## insure FXSAVE/FXRSTOR is enabled in CR4...
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## ... while we're at it, make sure DE is also enabled...
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mov $1, %eax
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pushl %ebx # temporarily save value of ebx on stack
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cpuid # use CPUID to determine if FXSAVE/FXRESTOR
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# and DE are supported
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popl %ebx # retore value of ebx that was overwritten
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# by CPUID
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movl %cr4, %eax
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orl $0x208,%eax
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pushl %eax # push cr4 firstly
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support
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jz L1
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orl $BIT9, %eax # Set CR4.OSFXSR
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L1:
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testl $BIT2, %edx # Test for Debugging Extensions support
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jz L2
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orl $BIT3, %eax # Set CR4.DE
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L2:
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movl %eax, %cr4
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pushl %eax
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movl %cr3, %eax
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pushl %eax
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movl %cr2, %eax
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@ -303,7 +318,11 @@ NoExtrPush:
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## FX_SAVE_STATE_IA32 FxSaveState;
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subl $512,%esp
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movl %esp,%edi
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support.
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# edx still contains result from CPUID above
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jz L3
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.byte 0x0f, 0xae, 0x07 # fxsave [edi]
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L3:
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## save the exception data
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pushl 8(%esp)
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@ -322,7 +341,13 @@ NoExtrPush:
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## FX_SAVE_STATE_IA32 FxSaveState;
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movl %esp,%esi
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movl $1, %eax
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cpuid # use CPUID to determine if FXSAVE/FXRESTOR
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# are supported
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testl $BIT24, %edx # Test for FXSAVE/FXRESTOR support
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jz L4
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.byte 0x0f, 0xae, 0x0e # fxrstor [esi]
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L4:
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addl $512,%esp
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## UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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@ -230,9 +230,21 @@ NoExtrPush:
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;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;
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;; insure FXSAVE/FXRSTOR is enabled in CR4...
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;; ... while we're at it, make sure DE is also enabled...
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mov eax, 1
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push ebx ; temporarily save value of ebx on stack
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cpuid ; use CPUID to determine if FXSAVE/FXRESTOR and
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; DE are supported
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pop ebx ; retore value of ebx that was overwritten by CPUID
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mov eax, cr4
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push eax ; push cr4 firstly
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or eax, 208h
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
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jz @F
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or eax, BIT9 ; Set CR4.OSFXSR
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@@:
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test edx, BIT2 ; Test for Debugging Extensions support
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jz @F
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or eax, BIT3 ; Set CR4.DE
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@@:
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mov cr4, eax
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mov eax, cr3
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push eax
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@ -313,7 +325,12 @@ NoExtrPush:
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mov ecx, 128 ;= 512 / 4
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rep stosd
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mov edi, esp
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support.
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; edx still contains result from CPUID above
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jz @F
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db 0fh, 0aeh, 00000111y ;fxsave [edi]
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@@:
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;; save the exception data
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push dword ptr [ebp + 8]
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@ -329,7 +346,12 @@ NoExtrPush:
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;; FX_SAVE_STATE_IA32 FxSaveState;
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mov esi, esp
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mov eax, 1
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cpuid ; use CPUID to determine if FXSAVE/FXRESTOR are supported
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test edx, BIT24 ; Test for FXSAVE/FXRESTOR support
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jz @F
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db 0fh, 0aeh, 00001110y ; fxrstor [esi]
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@@:
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add esp, 512
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;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
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@ -1,7 +1,7 @@
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/** @file
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Supporting functions for X64 architecture.
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Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -28,6 +28,7 @@ InitializeDebugIdt (
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IA32_DESCRIPTOR IdtDescriptor;
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UINTN Index;
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UINT16 CodeSegment;
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UINT32 RegEdx;
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AsmReadIdtr (&IdtDescriptor);
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@ -61,10 +62,14 @@ InitializeDebugIdt (
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IdtEntry[DEBUG_TIMER_VECTOR].Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
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//
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// If the CPU supports Debug Extensions(CPUID:01 EDX:BIT2), then
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// Set DE flag in CR4 to enable IO breakpoint
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//
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AsmCpuid (1, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT2) != 0) {
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AsmWriteCr4 (AsmReadCr4 () | BIT3);
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}
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}
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/**
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Retrieve exception handler from IDT table by ExceptionNum.
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@ -1,7 +1,7 @@
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## @file
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# Debug Agent library instance for Dxe Core and Dxe modules.
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#
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# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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MODULE_UNI_FILE = DxeDebugAgentLib.uni
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FILE_GUID = BA6BAD25-B814-4747-B0B0-0FBB61D40B90
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 0.7
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VERSION_STRING = 0.8
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LIBRARY_CLASS = DebugAgentLib|DXE_CORE DXE_DRIVER
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CONSTRUCTOR = DxeDebugAgentLibConstructor
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## @file
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# Debug Agent library instance for SEC Core and PEI modules.
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#
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# Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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MODULE_UNI_FILE = SecPeiDebugAgentLib.uni
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FILE_GUID = 508B7D59-CD4E-4a6b-A45B-6D3B2D90111E
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MODULE_TYPE = PEIM
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VERSION_STRING = 0.7
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VERSION_STRING = 0.8
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LIBRARY_CLASS = DebugAgentLib|SEC PEIM
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#
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MODULE_UNI_FILE = SmmDebugAgentLib.uni
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FILE_GUID = CB07D74C-598F-4268-A5D1-644FB4A481E8
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MODULE_TYPE = DXE_SMM_DRIVER
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VERSION_STRING = 0.7
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VERSION_STRING = 0.8
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LIBRARY_CLASS = DebugAgentLib|DXE_SMM_DRIVER
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#
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