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Add generic HPET Timer DXE Driver and support libraries 

Signed-off-by: mdkinney
Reviewed-by: li-elvin

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12259 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
mdkinney 2011-09-02 02:42:19 +00:00
parent 5244f47e46
commit 5f867ad00d
4 changed files with 238 additions and 4 deletions
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51
UefiCpuPkg/Include/Library/LocalApicLib.h
View File

@ -4,7 +4,7 @@
Local APIC library assumes local APIC is enabled. It does not Local APIC library assumes local APIC is enabled. It does not
handles cases where local APIC is disabled. handles cases where local APIC is disabled.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR> Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -319,5 +319,54 @@ SendApicEoi (
VOID VOID
); );
/**
Get the 32-bit address that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
@return 32-bit address used to send an MSI to the Local APIC.
**/
UINT32
EFIAPI
GetApicMsiAddress (
VOID
);
/**
Get the 64-bit data value that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
If Vector is not in range 0x10..0xFE, then ASSERT().
If DeliveryMode is not supported, then ASSERT().
@param Vector The 8-bit interrupt vector associated with the MSI.
Must be in the range 0x10..0xFE
@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
is handled. The only supported values are:
0: LOCAL_APIC_DELIVERY_MODE_FIXED
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
2: LOCAL_APIC_DELIVERY_MODE_SMI
4: LOCAL_APIC_DELIVERY_MODE_NMI
5: LOCAL_APIC_DELIVERY_MODE_INIT
7: LOCAL_APIC_DELIVERY_MODE_EXTINT
@param LevelTriggered TRUE specifies a level triggered interrupt.
FALSE specifies an edge triggered interrupt.
@param AssertionLevel Ignored if LevelTriggered is FALSE.
TRUE specifies a level triggered interrupt that active
when the interrupt line is asserted.
FALSE specifies a level triggered interrupt that active
when the interrupt line is deasserted.
@return 64-bit data value used to send an MSI to the Local APIC.
**/
UINT64
EFIAPI
GetApicMsiValue (
IN UINT8 Vector,
IN UINTN DeliveryMode,
IN BOOLEAN LevelTriggered,
IN BOOLEAN AssertionLevel
);
#endif #endif

33
UefiCpuPkg/Include/Register/LocalApic.h
View File

@ -1,7 +1,7 @@
/** @file /** @file
IA32 Local APIC Definitions. IA32 Local APIC Definitions.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR> Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -179,5 +179,36 @@ typedef union {
UINT32 Uint32; UINT32 Uint32;
} LOCAL_APIC_LVT_LINT; } LOCAL_APIC_LVT_LINT;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Reserved0:2; ///< Reserved
UINT32 DestinationMode:1; ///< Specifies the Destination Mode.
UINT32 RedirectionHint:1; ///< Specifies the Redirection Hint.
UINT32 Reserved1:8; ///< Reserved.
UINT32 DestinationId:8; ///< Specifies the Destination ID.
UINT32 BaseAddress:12; ///< Must be 0FEEH
} Bits;
UINT32 Uint32;
} LOCAL_APIC_MSI_ADDRESS;
//
// MSI Address Register
//
typedef union {
struct {
UINT32 Vector:8; ///< Interrupt vector in range 010h..0FEH
UINT32 DeliveryMode:3; ///< Specifies the type of interrupt to be sent.
UINT32 Reserved0:3; ///< Reserved.
UINT32 Level:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
UINT32 TriggerMode:1; ///< 0:Edge, 1:Level.
UINT32 Reserved1:16; ///< Reserved.
UINT32 Reserved2:32; ///< Reserved.
} Bits;
UINT64 Uint64;
} LOCAL_APIC_MSI_DATA;
#endif #endif

79
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
View File

@ -3,7 +3,7 @@
This local APIC library instance supports xAPIC mode only. This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR> Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -675,3 +675,80 @@ SendApicEoi (
WriteLocalApicReg (XAPIC_EOI_OFFSET, 0); WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
} }
/**
Get the 32-bit address that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
@return 32-bit address used to send an MSI to the Local APIC.
**/
UINT32
EFIAPI
GetApicMsiAddress (
VOID
)
{
LOCAL_APIC_MSI_ADDRESS MsiAddress;
//
// Return address for an MSI interrupt to be delivered only to the APIC ID
// of the currently executing processor.
//
MsiAddress.Uint32 = 0;
MsiAddress.Bits.BaseAddress = 0xFEE;
MsiAddress.Bits.DestinationId = GetApicId ();
return MsiAddress.Uint32;
}
/**
Get the 64-bit data value that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
If Vector is not in range 0x10..0xFE, then ASSERT().
If DeliveryMode is not supported, then ASSERT().
@param Vector The 8-bit interrupt vector associated with the MSI.
Must be in the range 0x10..0xFE
@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
is handled. The only supported values are:
0: LOCAL_APIC_DELIVERY_MODE_FIXED
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
2: LOCAL_APIC_DELIVERY_MODE_SMI
4: LOCAL_APIC_DELIVERY_MODE_NMI
5: LOCAL_APIC_DELIVERY_MODE_INIT
7: LOCAL_APIC_DELIVERY_MODE_EXTINT
@param LevelTriggered TRUE specifies a level triggered interrupt.
FALSE specifies an edge triggered interrupt.
@param AssertionLevel Ignored if LevelTriggered is FALSE.
TRUE specifies a level triggered interrupt that active
when the interrupt line is asserted.
FALSE specifies a level triggered interrupt that active
when the interrupt line is deasserted.
@return 64-bit data value used to send an MSI to the Local APIC.
**/
UINT64
EFIAPI
GetApicMsiValue (
IN UINT8 Vector,
IN UINTN DeliveryMode,
IN BOOLEAN LevelTriggered,
IN BOOLEAN AssertionLevel
)
{
LOCAL_APIC_MSI_DATA MsiData;
ASSERT (Vector >= 0x10 && Vector <= 0xFE);
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
MsiData.Uint64 = 0;
MsiData.Bits.Vector = Vector;
MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
if (LevelTriggered) {
MsiData.Bits.TriggerMode = 1;
if (AssertionLevel) {
MsiData.Bits.Level = 1;
}
}
return MsiData.Uint64;
}

79
UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
View File

@ -4,7 +4,7 @@
This local APIC library instance supports x2APIC capable processors This local APIC library instance supports x2APIC capable processors
which have xAPIC and x2APIC modes. which have xAPIC and x2APIC modes.
Copyright (c) 2010, Intel Corporation. All rights reserved.<BR> Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -758,3 +758,80 @@ SendApicEoi (
WriteLocalApicReg (XAPIC_EOI_OFFSET, 0); WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);
} }
/**
Get the 32-bit address that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
@return 32-bit address used to send an MSI to the Local APIC.
**/
UINT32
EFIAPI
GetApicMsiAddress (
VOID
)
{
LOCAL_APIC_MSI_ADDRESS MsiAddress;
//
// Return address for an MSI interrupt to be delivered only to the APIC ID
// of the currently executing processor.
//
MsiAddress.Uint32 = 0;
MsiAddress.Bits.BaseAddress = 0xFEE;
MsiAddress.Bits.DestinationId = GetApicId ();
return MsiAddress.Uint32;
}
/**
Get the 64-bit data value that a device should use to send a Message Signaled
Interrupt (MSI) to the Local APIC of the currently executing processor.
If Vector is not in range 0x10..0xFE, then ASSERT().
If DeliveryMode is not supported, then ASSERT().
@param Vector The 8-bit interrupt vector associated with the MSI.
Must be in the range 0x10..0xFE
@param DeliveryMode A 3-bit value that specifies how the recept of the MSI
is handled. The only supported values are:
0: LOCAL_APIC_DELIVERY_MODE_FIXED
1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
2: LOCAL_APIC_DELIVERY_MODE_SMI
4: LOCAL_APIC_DELIVERY_MODE_NMI
5: LOCAL_APIC_DELIVERY_MODE_INIT
7: LOCAL_APIC_DELIVERY_MODE_EXTINT
@param LevelTriggered TRUE specifies a level triggered interrupt.
FALSE specifies an edge triggered interrupt.
@param AssertionLevel Ignored if LevelTriggered is FALSE.
TRUE specifies a level triggered interrupt that active
when the interrupt line is asserted.
FALSE specifies a level triggered interrupt that active
when the interrupt line is deasserted.
@return 64-bit data value used to send an MSI to the Local APIC.
**/
UINT64
EFIAPI
GetApicMsiValue (
IN UINT8 Vector,
IN UINTN DeliveryMode,
IN BOOLEAN LevelTriggered,
IN BOOLEAN AssertionLevel
)
{
LOCAL_APIC_MSI_DATA MsiData;
ASSERT (Vector >= 0x10 && Vector <= 0xFE);
ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);
MsiData.Uint64 = 0;
MsiData.Bits.Vector = Vector;
MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;
if (LevelTriggered) {
MsiData.Bits.TriggerMode = 1;
if (AssertionLevel) {
MsiData.Bits.Level = 1;
}
}
return MsiData.Uint64;
}