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Ring3: Added support for AARCH64 EL2&0 translation regime.
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3cab34a4ba
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6012848e12
@ -23,6 +23,7 @@
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// Coprocessor Trap Register (CPTR)
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// Coprocessor Trap Register (CPTR)
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#define AARCH64_CPTR_TFP (1 << 10)
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#define AARCH64_CPTR_TFP (1 << 10)
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#define AARCH64_CPTR_FPEN (3 << 20)
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// ID_AA64MMFR1 - AArch64 Memory Model Feature Register 0 definitions
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// ID_AA64MMFR1 - AArch64 Memory Model Feature Register 0 definitions
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#define AARCH64_MMFR1_VH (0xF << 8)
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#define AARCH64_MMFR1_VH (0xF << 8)
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@ -44,6 +45,9 @@
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#define SCR_FW (1 << 4)
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#define SCR_FW (1 << 4)
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#define SCR_AW (1 << 5)
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#define SCR_AW (1 << 5)
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// SCTLR - System Control Register definitions
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#define SCTLR_EPAN BIT57
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// MIDR - Main ID Register definitions
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// MIDR - Main ID Register definitions
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#define ARM_CPU_TYPE_SHIFT 4
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#define ARM_CPU_TYPE_SHIFT 4
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#define ARM_CPU_TYPE_MASK 0xFFF
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#define ARM_CPU_TYPE_MASK 0xFFF
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@ -65,6 +69,7 @@
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#define ARM_HCR_AMO BIT5
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#define ARM_HCR_AMO BIT5
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#define ARM_HCR_TSC BIT19
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#define ARM_HCR_TSC BIT19
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#define ARM_HCR_TGE BIT27
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#define ARM_HCR_TGE BIT27
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#define ARM_HCR_E2H BIT34
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// Exception Syndrome Register
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// Exception Syndrome Register
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#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
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#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
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@ -551,7 +551,7 @@ ArmWriteMVBar (
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IN UINT32 VectorMonitorBase
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IN UINT32 VectorMonitorBase
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);
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);
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UINT32
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UINTN
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EFIAPI
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EFIAPI
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ArmReadSctlr (
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ArmReadSctlr (
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VOID
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VOID
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@ -560,7 +560,7 @@ ArmReadSctlr (
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VOID
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VOID
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EFIAPI
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EFIAPI
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ArmWriteSctlr (
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ArmWriteSctlr (
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IN UINT32 Value
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IN UINTN Value
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);
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);
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UINTN
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UINTN
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@ -149,7 +149,12 @@ ASM_FUNC(ArmInvalidateTlb)
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ret
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ret
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ASM_FUNC(ArmWriteCptr)
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ASM_FUNC(ArmWriteCptr)
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msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)
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EL1_OR_EL2_OR_EL3(x1)
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1:ret
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2:msr cptr_el2, x0
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b 4f
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3:msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)
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4:isb
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ret
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ret
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ASM_FUNC(ArmWriteScr)
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ASM_FUNC(ArmWriteScr)
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@ -39,13 +39,9 @@ ArmMemoryAttributeToPageAttribute (
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP:
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case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_XP:
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case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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if (ArmReadCurrentEL () == AARCH64_EL2) {
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Permissions = TT_UXN_MASK | TT_PXN_MASK;
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Permissions = TT_XN_MASK;
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} else {
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Permissions = TT_UXN_MASK | TT_PXN_MASK;
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}
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break;
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break;
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default:
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default:
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Permissions = 0;
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Permissions = 0;
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break;
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break;
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@ -444,11 +440,7 @@ GcdAttributeToPageAttribute (
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if (((GcdAttributes & EFI_MEMORY_XP) != 0) ||
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if (((GcdAttributes & EFI_MEMORY_XP) != 0) ||
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((GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC))
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((GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC))
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{
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{
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if (ArmReadCurrentEL () == AARCH64_EL2) {
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PageAttributes |= TT_UXN_MASK | TT_PXN_MASK;
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PageAttributes |= TT_XN_MASK;
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} else {
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PageAttributes |= TT_UXN_MASK | TT_PXN_MASK;
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}
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}
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}
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if ((GcdAttributes & EFI_MEMORY_RP) == 0) {
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if ((GcdAttributes & EFI_MEMORY_RP) == 0) {
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@ -464,12 +456,7 @@ GcdAttributeToPageAttribute (
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PageAttributes |= TT_AP_RW_RW;
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PageAttributes |= TT_AP_RW_RW;
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}
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}
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} else {
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} else {
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if (ArmReadCurrentEL () == AARCH64_EL1) {
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PageAttributes |= TT_UXN_MASK;
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//
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// TODO: Add EL2&0 support.
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//
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PageAttributes |= TT_UXN_MASK;
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}
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if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
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if ((GcdAttributes & EFI_MEMORY_RO) != 0) {
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PageAttributes |= TT_AP_NO_RO;
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PageAttributes |= TT_AP_NO_RO;
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@ -579,6 +566,7 @@ ArmConfigureMmu (
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UINTN RootTableEntryCount;
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UINTN RootTableEntryCount;
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UINT64 TCR;
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UINT64 TCR;
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EFI_STATUS Status;
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EFI_STATUS Status;
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UINTN Hcr;
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if (MemoryTable == NULL) {
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if (MemoryTable == NULL) {
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ASSERT (MemoryTable != NULL);
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ASSERT (MemoryTable != NULL);
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@ -598,38 +586,25 @@ ArmConfigureMmu (
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T0SZ = 64 - MaxAddressBits;
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T0SZ = 64 - MaxAddressBits;
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RootTableEntryCount = GetRootTableEntryCount (T0SZ);
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RootTableEntryCount = GetRootTableEntryCount (T0SZ);
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if (ArmReadCurrentEL () == AARCH64_EL2) {
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//
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// Switch to EL2&0 translation regime.
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//
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Hcr = ArmReadHcr ();
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Hcr |= ARM_HCR_E2H | ARM_HCR_TGE;
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ArmWriteHcr (Hcr);
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//
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// Allow access to the Advanced SIMD and floating-point registers.
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//
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ArmWriteCptr (AARCH64_CPTR_FPEN);
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}
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//
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//
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// Set TCR that allows us to retrieve T0SZ in the subsequent functions
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// Set TCR that allows us to retrieve T0SZ in the subsequent functions
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//
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//
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// Ideally we will be running at EL2, but should support EL1 as well.
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// Ideally we will be running at EL2, but should support EL1 as well.
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// UEFI should not run at EL3.
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// UEFI should not run at EL3.
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if (ArmReadCurrentEL () == AARCH64_EL2) {
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if ((ArmReadCurrentEL () == AARCH64_EL1) || (ArmReadCurrentEL () == AARCH64_EL2)) {
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// Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
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TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
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// Set the Physical Address Size using MaxAddress
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if (MaxAddress < SIZE_4GB) {
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TCR |= TCR_PS_4GB;
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} else if (MaxAddress < SIZE_64GB) {
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TCR |= TCR_PS_64GB;
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} else if (MaxAddress < SIZE_1TB) {
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TCR |= TCR_PS_1TB;
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} else if (MaxAddress < SIZE_4TB) {
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TCR |= TCR_PS_4TB;
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} else if (MaxAddress < SIZE_16TB) {
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TCR |= TCR_PS_16TB;
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} else if (MaxAddress < SIZE_256TB) {
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TCR |= TCR_PS_256TB;
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} else {
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DEBUG ((
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DEBUG_ERROR,
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"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
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MaxAddress
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));
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ASSERT (0); // Bigger than 48-bit memory space are not supported
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return EFI_UNSUPPORTED;
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}
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} else if (ArmReadCurrentEL () == AARCH64_EL1) {
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// Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.
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// Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.
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TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;
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TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;
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@ -106,7 +106,7 @@
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ArmGicArchLib|ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.inf
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ArmGicArchLib|ArmVirtPkg/Library/ArmVirtGicArchLib/ArmVirtGicArchLib.inf
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ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
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ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
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ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
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ArmHvcLib|ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf
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ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.inf
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ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
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PlatformPeiLib|ArmVirtPkg/Library/PlatformPeiLib/PlatformPeiLib.inf
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PlatformPeiLib|ArmVirtPkg/Library/PlatformPeiLib/PlatformPeiLib.inf
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MemoryInitPeiLib|ArmVirtPkg/Library/ArmVirtMemoryInitPeiLib/ArmVirtMemoryInitPeiLib.inf
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MemoryInitPeiLib|ArmVirtPkg/Library/ArmVirtMemoryInitPeiLib/ArmVirtMemoryInitPeiLib.inf
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@ -88,24 +88,23 @@ ASM_FUNC(ArmCallRing3)
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// Disable interrupts.
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// Disable interrupts.
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msr daifset, #0xf
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msr daifset, #0xf
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isb
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isb
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// Copy PSTATE to SPSR.
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mrs x6, nzcv
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mrs x7, pan
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orr x6, x6, x7
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// Prepare Ring3 SP and EntryPoint.
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// Prepare Ring3 SP and EntryPoint.
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msr sp_el0, x1
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msr sp_el0, x1
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msr elr_el1, x2
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EL1_OR_EL2(x1)
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1:msr elr_el1, x2
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msr spsr_el1, x6
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b 3f
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2:msr elr_el2, x2
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msr spsr_el2, x6
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// Save Core SP and switch to CoreSysCall Stack.
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// Save Core SP and switch to CoreSysCall Stack.
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mov x5, sp
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3:mov x5, sp
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str x5, [x4]
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str x5, [x4]
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mov sp, x3
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mov sp, x3
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// Copy PSTATE to SPSR.
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mrs x1, nzcv
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mrs x2, pan
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orr x1, x1, x2
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//
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// M[3:0], bits [3:0] AArch64 Exception level and selected Stack Pointer.
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// 0b0000 - EL0.
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// 0b0100 - EL1 with SP_EL0 (ELt).
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// 0b0101 - EL1 with SP_EL1 (EL1h).
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//
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msr spsr_el1, x1
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isb
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isb
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eret
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eret
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@ -97,6 +97,7 @@ InitializeMsr (
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)
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)
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{
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{
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UINTN Tcr;
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UINTN Tcr;
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UINTN Sctlr;
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//
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//
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// If HCR_EL2.NV is 1 and the current Exception level is EL1,
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// If HCR_EL2.NV is 1 and the current Exception level is EL1,
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// then EL1 read accesses to the CurrentEL register return a value of 0x2 in bits[3:2].
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// then EL1 read accesses to the CurrentEL register return a value of 0x2 in bits[3:2].
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@ -115,6 +116,10 @@ InitializeMsr (
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//
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//
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// Enable Privileged Access Never feature.
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// Enable Privileged Access Never feature.
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//
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//
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Sctlr = ArmReadSctlr ();
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Sctlr |= SCTLR_EPAN;
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ArmWriteSctlr (Sctlr);
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ArmSetPan ();
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ArmSetPan ();
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}
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}
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