mirror of https://github.com/acidanthera/audk.git
OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly
In the MemMapInitialization() function, we currently have a common PciSize assignment, shared between i440fx and q35. In order to simplify the rest of this series, lift and duplicate the assignment identically to both board-specific branches. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1814 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1666941 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1701710 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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@ -190,8 +190,10 @@ MemMapInitialization (
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ASSERT (TopOfLowRam <= PciExBarBase);
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ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
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PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
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PciSize = 0xFC000000 - PciBase;
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} else {
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PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
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PciSize = 0xFC000000 - PciBase;
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}
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//
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@ -207,7 +209,6 @@ MemMapInitialization (
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// 0xFED20000 gap 896 KB
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// 0xFEE00000 LAPIC 1 MB
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//
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PciSize = 0xFC000000 - PciBase;
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AddIoMemoryBaseSizeHob (PciBase, PciSize);
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PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);
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ASSERT_RETURN_ERROR (PcdStatus);
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