mirror of https://github.com/acidanthera/audk.git
MdePkg/IndustryStandard: Add SD/EMMC common definitions
These definitions are defined in SD physical layer simplified spec and eMMC electrical standard spec. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
This commit is contained in:
Feng Tian
parent
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/** @file
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Header file for eMMC support.
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This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec.
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Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __EMMC_H__
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#define __EMMC_H__
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//
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// EMMC command index
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//
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#define EMMC_GO_IDLE_STATE 0
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#define EMMC_SEND_OP_COND 1
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#define EMMC_ALL_SEND_CID 2
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#define EMMC_SET_RELATIVE_ADDR 3
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#define EMMC_SET_DSR 4
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#define EMMC_SLEEP_AWAKE 5
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#define EMMC_SWITCH 6
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#define EMMC_SELECT_DESELECT_CARD 7
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#define EMMC_SEND_EXT_CSD 8
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#define EMMC_SEND_CSD 9
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#define EMMC_SEND_CID 10
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#define EMMC_STOP_TRANSMISSION 12
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#define EMMC_SEND_STATUS 13
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#define EMMC_BUSTEST_R 14
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#define EMMC_GO_INACTIVE_STATE 15
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#define EMMC_SET_BLOCKLEN 16
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#define EMMC_READ_SINGLE_BLOCK 17
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#define EMMC_READ_MULTIPLE_BLOCK 18
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#define EMMC_BUSTEST_W 19
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#define EMMC_SEND_TUNING_BLOCK 21
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#define EMMC_SET_BLOCK_COUNT 23
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#define EMMC_WRITE_BLOCK 24
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#define EMMC_WRITE_MULTIPLE_BLOCK 25
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#define EMMC_PROGRAM_CID 26
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#define EMMC_PROGRAM_CSD 27
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#define EMMC_SET_WRITE_PROT 28
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#define EMMC_CLR_WRITE_PROT 29
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#define EMMC_SEND_WRITE_PROT 30
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#define EMMC_SEND_WRITE_PROT_TYPE 31
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#define EMMC_ERASE_GROUP_START 35
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#define EMMC_ERASE_GROUP_END 36
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#define EMMC_ERASE 38
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#define EMMC_FAST_IO 39
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#define EMMC_GO_IRQ_STATE 40
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#define EMMC_LOCK_UNLOCK 42
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#define EMMC_SET_TIME 49
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#define EMMC_PROTOCOL_RD 53
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#define EMMC_PROTOCOL_WR 54
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#define EMMC_APP_CMD 55
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#define EMMC_GEN_CMD 56
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typedef enum {
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EmmcPartitionUserData = 0,
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EmmcPartitionBoot1 = 1,
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EmmcPartitionBoot2 = 2,
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EmmcPartitionRPMB = 3,
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EmmcPartitionGP1 = 4,
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EmmcPartitionGP2 = 5,
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EmmcPartitionGP3 = 6,
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EmmcPartitionGP4 = 7,
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EmmcPartitionUnknown
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} EMMC_PARTITION_TYPE;
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#pragma pack(1)
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typedef struct {
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UINT8 NotUsed:1; // Not used [0:0]
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UINT8 Crc:7; // CRC [7:1]
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UINT8 ManufacturingDate; // Manufacturing date [15:8]
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UINT8 ProductSerialNumber[4]; // Product serial number [47:16]
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UINT8 ProductRevision; // Product revision [55:48]
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UINT8 ProductName[6]; // Product name [103:56]
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UINT8 OemId; // OEM/Application ID [111:104]
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UINT8 DeviceType:2; // Device/BGA [113:112]
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UINT8 Reserved:6; // Reserved [119:114]
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UINT8 ManufacturerId; // Manufacturer ID [127:120]
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} EMMC_CID;
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typedef struct {
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UINT32 NotUsed:1; // Not used [0:0]
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UINT32 Crc:7; // CRC [7:1]
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UINT32 Ecc:2; // ECC code [9:8]
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UINT32 FileFormat:2; // File format [11:10]
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UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
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UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
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UINT32 Copy:1; // Copy flag (OTP) [14:14]
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UINT32 FileFormatGrp:1; // File format group [15:15]
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UINT32 ContentProtApp:1; // Content protection application [16:16]
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UINT32 Reserved:4; // Reserved [20:17]
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UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
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UINT32 WriteBlLen:4; // Max. write data block length [25:22]
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UINT32 R2WFactor:3; // Write speed factor [28:26]
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UINT32 DefaultEcc:2; // Manufacturer default ECC [30:29]
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UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
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UINT32 WpGrpSize:5; // Write protect group size [36:32]
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UINT32 EraseGrpMult:5; // Erase group size multiplier [41:37]
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UINT32 EraseGrpSize:5; // Erase group size [46:42]
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UINT32 CSizeMult:3; // Device size multiplier [49:47]
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UINT32 VddWCurrMax:3; // Max. write current @ VDD max [52:50]
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UINT32 VddWCurrMin:3; // Max. write current @ VDD min [55:53]
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UINT32 VddRCurrMax:3; // Max. read current @ VDD max [58:56]
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UINT32 VddRCurrMin:3; // Max. read current @ VDD min [61:59]
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UINT32 CSizeLow:2; // Device size low two bits [63:62]
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UINT32 CSizeHigh:10; // Device size high eight bits [73:64]
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UINT32 Reserved1:2; // Reserved [75:74]
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UINT32 DsrImp:1; // DSR implemented [76:76]
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UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
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UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
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UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
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UINT32 ReadBlLen:4; // Max. read data block length [83:80]
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UINT32 Ccc:12; // Device command classes [95:84]
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UINT32 TranSpeed:8; // Max. bus clock frequency [103:96]
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UINT32 Nsac:8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
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UINT32 Taac:8; // Data read access-time 1 [119:112]
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UINT32 Reserved2:2; // Reserved [121:120]
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UINT32 SpecVers:4; // System specification version [125:122]
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UINT32 CsdStructure:2; // CSD structure [127:126]
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} EMMC_CSD;
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typedef struct {
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//
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// Modes Segment
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//
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UINT8 Reserved[16]; // Reserved [15:0]
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UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]
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UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]
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UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]
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UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]
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UINT8 FfuStatus; // FFU status R [26]
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UINT8 Reserved1[2]; // Reserved [28:27]
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UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]
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UINT8 ModeConfig; // Mode config R/W/EP [30]
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UINT8 Reserved2; // Reserved [31]
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UINT8 FlushCache; // Flushing of the cache W/EP [32]
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UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]
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UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]
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UINT8 PackedFailureIndex; // Packed command failure index R [35]
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UINT8 PackedCommandStatus; // Packed command status R [36]
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UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]
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UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]
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UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]
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UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]
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UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]
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UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]
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UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]
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UINT8 DataSectorSize; // Sector size R [61]
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UINT8 UseNativeSector; // Sector size emulation R/W [62]
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UINT8 NativeSectorSize; // Native sector size R [63]
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UINT8 VendorSpecificField[64]; // Vendor Specific Fields <vendor specific> [127:64]
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UINT8 Reserved3[2]; // Reserved [129:128]
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UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]
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UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]
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UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]
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UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]
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UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]
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UINT8 Reserved4; // Reserved [135]
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UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]
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UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]
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UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]
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UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]
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UINT8 PartitionsAttribute; // Partitions attribute R/W [156]
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UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]
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UINT8 PartitioningSupport; // Partitioning Support R [160]
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UINT8 HpiMgmt; // HPI management R/W/EP [161]
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UINT8 RstFunction; // H/W reset function R/W [162]
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UINT8 BkopsEn; // Enable background operations handshake R/W [163]
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UINT8 BkopsStart; // Manually start background operations W/EP [164]
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UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]
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UINT8 WrRelParam; // Write reliability parameter register R [166]
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UINT8 WrRelSet; // Write reliability setting register R/W [167]
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UINT8 RpmbSizeMult; // RPMB Size R [168]
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UINT8 FwConfig; // FW configuration R/W [169]
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UINT8 Reserved5; // Reserved [170]
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UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]
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UINT8 Reserved6; // Reserved [172]
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UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]
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UINT8 BootWpStatus; // Boot write protection status registers R [174]
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UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]
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UINT8 Reserved7; // Reserved [176]
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UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]
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UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]
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UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]
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UINT8 Reserved8; // Reserved [180]
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UINT8 ErasedMemCont; // Erased memory content R [181]
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UINT8 Reserved9; // Reserved [182]
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UINT8 BusWidth; // Bus width mode W/EP [183]
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UINT8 Reserved10; // Reserved [184]
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UINT8 HsTiming; // High-speed interface timing R/W/EP [185]
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UINT8 Reserved11; // Reserved [186]
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UINT8 PowerClass; // Power class R/W/EP [187]
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UINT8 Reserved12; // Reserved [188]
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UINT8 CmdSetRev; // Command set revision R [189]
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UINT8 Reserved13; // Reserved [190]
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UINT8 CmdSet; // Command set R/W/EP [191]
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//
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// Properties Segment
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//
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UINT8 ExtCsdRev; // Extended CSD revision [192]
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UINT8 Reserved14; // Reserved [193]
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UINT8 CsdStructure; // CSD STRUCTURE [194]
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UINT8 Reserved15; // Reserved [195]
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UINT8 DeviceType; // Device type [196]
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UINT8 DriverStrength; // I/O Driver Strength [197]
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UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]
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UINT8 PartitionSwitchTime; // Partition switching timing [199]
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UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]
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UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]
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UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]
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UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]
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UINT8 Reserved16; // Reserved [204]
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UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]
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UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]
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UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]
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UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]
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UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]
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UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]
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UINT8 Reserved17; // Reserved [211]
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UINT8 SecCount[4]; // Sector Count [215:212]
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UINT8 SleepNotificationTime; // Sleep Notification Timout [216]
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UINT8 SATimeout; // Sleep/awake timeout [217]
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UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]
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UINT8 SCVccq; // Sleep current (VCCQ) [219]
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UINT8 SCVcc; // Sleep current (VCC) [220]
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UINT8 HcWpGrpSize; // High-capacity write protect group size [221]
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UINT8 RelWrSecC; // Reliable write sector count [222]
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UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]
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UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]
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UINT8 AccSize; // Access size [225]
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UINT8 BootSizeMult; // Boot partition size [226]
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UINT8 Reserved18; // Reserved [227]
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UINT8 BootInfo; // Boot information [228]
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UINT8 SecTrimMult; // Secure TRIM Multiplier [229]
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UINT8 SecEraseMult; // Secure Erase Multiplier [230]
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UINT8 SecFeatureSupport; // Secure Feature support [231]
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UINT8 TrimMult; // TRIM Multiplier [232]
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UINT8 Reserved19; // Reserved [233]
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UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]
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UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]
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UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]
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UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]
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UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]
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UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]
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UINT8 Reserved20; // Reserved [240]
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UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]
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UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]
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UINT8 BkopsStatus; // Background operations status [246]
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UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]
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UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]
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UINT8 CacheSize[4]; // Cache size [252:249]
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UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]
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UINT8 FirmwareVersion[8]; // Firmware version [261:254]
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UINT8 DeviceVersion[2]; // Device version [263:262]
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UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]
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UINT8 OptimalWriteSize; // Optimal write size [265]
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UINT8 OptimalReadSize; // Optimal read size [266]
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UINT8 PreEolInfo; // Pre EOL information [267]
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UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]
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UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]
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UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]
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UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]
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UINT8 Reserved21[181]; // Reserved [486:306]
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UINT8 FfuArg[4]; // FFU Argument [490:487]
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UINT8 OperationCodeTimeout; // Operation codes timeout [491]
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UINT8 FfuFeatures; // FFU features [492]
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UINT8 SupportedModes; // Supported modes [493]
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UINT8 ExtSupport; // Extended partitions attribute support [494]
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UINT8 LargeUnitSizeM1; // Large Unit size [495]
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UINT8 ContextCapabilities; // Context management capabilities [496]
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UINT8 TagResSize; // Tag Resources Size [497]
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UINT8 TagUnitSize; // Tag Unit Size [498]
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UINT8 DataTagSupport; // Data Tag Support [499]
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UINT8 MaxPackedWrites; // Max packed write commands [500]
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UINT8 MaxPackedReads; // Max packed read commands[501]
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UINT8 BkOpsSupport; // Background operations support [502]
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UINT8 HpiFeatures; // HPI features [503]
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UINT8 SupportedCmdSet; // Supported Command Sets [504]
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UINT8 ExtSecurityErr; // Extended Security Commands Error [505]
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UINT8 Reserved22[6]; // Reserved [511:506]
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} EMMC_EXT_CSD;
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#pragma pack()
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#endif
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@ -0,0 +1,181 @@
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/** @file
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Header file for SD memory card support.
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This header file contains some definitions defined in SD Physical Layer Simplified
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Specification Version 4.10 spec.
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Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef __SD_H__
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#define __SD_H__
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//
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// SD command index
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//
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#define SD_GO_IDLE_STATE 0
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#define SD_ALL_SEND_CID 2
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#define SD_SET_RELATIVE_ADDR 3
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#define SD_SET_DSR 4
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#define SDIO_SEND_OP_COND 5
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#define SD_SWITCH_FUNC 6
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#define SD_SELECT_DESELECT_CARD 7
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#define SD_SEND_IF_COND 8
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#define SD_SEND_CSD 9
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#define SD_SEND_CID 10
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#define SD_VOLTAGE_SWITCH 11
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#define SD_STOP_TRANSMISSION 12
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#define SD_SEND_STATUS 13
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#define SD_GO_INACTIVE_STATE 15
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#define SD_SET_BLOCKLEN 16
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#define SD_READ_SINGLE_BLOCK 17
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#define SD_READ_MULTIPLE_BLOCK 18
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#define SD_SEND_TUNING_BLOCK 19
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#define SD_SPEED_CLASS_CONTROL 20
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#define SD_SET_BLOCK_COUNT 23
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#define SD_WRITE_SINGLE_BLOCK 24
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#define SD_WRITE_MULTIPLE_BLOCK 25
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#define SD_PROGRAM_CSD 27
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#define SD_SET_WRITE_PROT 28
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#define SD_CLR_WRITE_PROT 29
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#define SD_SEND_WRITE_PROT 30
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#define SD_ERASE_WR_BLK_START 32
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#define SD_ERASE_WR_BLK_END 33
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#define SD_ERASE 38
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#define SD_LOCK_UNLOCK 42
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#define SD_READ_EXTR_SINGLE 48
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#define SD_WRITE_EXTR_SINGLE 49
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#define SDIO_RW_DIRECT 52
|
||||
#define SDIO_RW_EXTENDED 53
|
||||
#define SD_APP_CMD 55
|
||||
#define SD_GEN_CMD 56
|
||||
#define SD_READ_EXTR_MULTI 58
|
||||
#define SD_WRITE_EXTR_MULTI 59
|
||||
|
||||
#define SD_SET_BUS_WIDTH 6 // ACMD6
|
||||
#define SD_STATUS 13 // ACMD13
|
||||
#define SD_SEND_NUM_WR_BLOCKS 22 // ACMD22
|
||||
#define SD_SET_WR_BLK_ERASE_COUNT 23 // ACMD23
|
||||
#define SD_SEND_OP_COND 41 // ACMD41
|
||||
#define SD_SET_CLR_CARD_DETECT 42 // ACMD42
|
||||
#define SD_SEND_SCR 51 // ACMD51
|
||||
|
||||
#pragma pack(1)
|
||||
typedef struct {
|
||||
UINT8 NotUsed:1; // Not used [0:0]
|
||||
UINT8 Crc:7; // CRC [7:1]
|
||||
UINT16 ManufacturingDate:12; // Manufacturing date [19:8]
|
||||
UINT16 Reserved:4; // Reserved [23:20]
|
||||
UINT8 ProductSerialNumber[4]; // Product serial number [55:24]
|
||||
UINT8 ProductRevision; // Product revision [63:56]
|
||||
UINT8 ProductName[5]; // Product name [103:64]
|
||||
UINT8 OemId[2]; // OEM/Application ID [119:104]
|
||||
UINT8 ManufacturerId; // Manufacturer ID [127:120]
|
||||
} SD_CID;
|
||||
|
||||
typedef struct {
|
||||
UINT32 NotUsed:1; // Not used [0:0]
|
||||
UINT32 Crc:7; // CRC [7:1]
|
||||
UINT32 Reserved:2; // Reserved [9:8]
|
||||
UINT32 FileFormat:2; // File format [11:10]
|
||||
UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
|
||||
UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
|
||||
UINT32 Copy:1; // Copy flag (OTP) [14:14]
|
||||
UINT32 FileFormatGrp:1; // File format group [15:15]
|
||||
UINT32 Reserved1:5; // Reserved [20:16]
|
||||
UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
|
||||
UINT32 WriteBlLen:4; // Max. write data block length [25:22]
|
||||
UINT32 R2WFactor:3; // Write speed factor [28:26]
|
||||
UINT32 Reserved2:2; // Manufacturer default ECC [30:29]
|
||||
UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
|
||||
|
||||
UINT32 WpGrpSize:7; // Write protect group size [38:32]
|
||||
UINT32 SectorSize:7; // Erase sector size [45:39]
|
||||
UINT32 EraseBlkEn:1; // Erase single block enable [46:46]
|
||||
UINT32 CSizeMul:3; // device size multiplier [49:47]
|
||||
UINT32 VddWCurrMax:3; // max. write current @VDD max [52:50]
|
||||
UINT32 VddWCurrMin:3; // max. write current @VDD min [55:53]
|
||||
UINT32 VddRCurrMax:3; // max. read current @VDD max [58:56]
|
||||
UINT32 VddRCurrMin:3; // max. read current @VDD min [61:59]
|
||||
UINT32 CSizeLow:2; // Device size low 2 bits [63:62]
|
||||
|
||||
UINT32 CSizeHigh:10; // Device size high 10 bits [73:64]
|
||||
UINT32 Reserved4:2; // Reserved [75:74]
|
||||
UINT32 DsrImp:1; // DSR implemented [76:76]
|
||||
UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
|
||||
UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
|
||||
UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
|
||||
UINT32 ReadBlLen:4; // Max. read data block length [83:80]
|
||||
UINT32 Ccc:12; // Card command classes [95:84]
|
||||
|
||||
UINT32 TranSpeed:8; // Max. data transfer rate [103:96]
|
||||
UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
|
||||
UINT32 Taac:8; // Data read access-time [119:112]
|
||||
UINT32 Reserved5:6; // Reserved [125:120]
|
||||
UINT32 CsdStructure:2; // CSD structure [127:126]
|
||||
} SD_CSD;
|
||||
|
||||
typedef struct {
|
||||
UINT32 NotUsed:1; // Not used [0:0]
|
||||
UINT32 Crc:7; // CRC [7:1]
|
||||
UINT32 Reserved:2; // Reserved [9:8]
|
||||
UINT32 FileFormat:2; // File format [11:10]
|
||||
UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]
|
||||
UINT32 PermWriteProtect:1; // Permanent write protection [13:13]
|
||||
UINT32 Copy:1; // Copy flag (OTP) [14:14]
|
||||
UINT32 FileFormatGrp:1; // File format group [15:15]
|
||||
UINT32 Reserved1:5; // Reserved [20:16]
|
||||
UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]
|
||||
UINT32 WriteBlLen:4; // Max. write data block length [25:22]
|
||||
UINT32 R2WFactor:3; // Write speed factor [28:26]
|
||||
UINT32 Reserved2:2; // Manufacturer default ECC [30:29]
|
||||
UINT32 WpGrpEnable:1; // Write protect group enable [31:31]
|
||||
|
||||
UINT32 WpGrpSize:7; // Write protect group size [38:32]
|
||||
UINT32 SectorSize:7; // Erase sector size [45:39]
|
||||
UINT32 EraseBlkEn:1; // Erase single block enable [46:46]
|
||||
UINT32 Reserved3:1; // Reserved [47:47]
|
||||
UINT32 CSizeLow:16; // Device size low 16 bits [63:48]
|
||||
|
||||
UINT32 CSizeHigh:6; // Device size high 6 bits [69:64]
|
||||
UINT32 Reserved4:6; // Reserved [75:70]
|
||||
UINT32 DsrImp:1; // DSR implemented [76:76]
|
||||
UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]
|
||||
UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]
|
||||
UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]
|
||||
UINT32 ReadBlLen:4; // Max. read data block length [83:80]
|
||||
UINT32 Ccc:12; // Card command classes [95:84]
|
||||
|
||||
UINT32 TranSpeed:8; // Max. data transfer rate [103:96]
|
||||
UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]
|
||||
UINT32 Taac:8; // Data read access-time [119:112]
|
||||
UINT32 Reserved5:6; // Reserved [125:120]
|
||||
UINT32 CsdStructure:2; // CSD structure [127:126]
|
||||
} SD_CSD2;
|
||||
|
||||
typedef struct {
|
||||
UINT32 Reserved; // Reserved [31:0]
|
||||
|
||||
UINT32 CmdSupport:4; // Command Support bits [35:32]
|
||||
UINT32 Reserved1:6; // Reserved [41:36]
|
||||
UINT32 SdSpec4:1; // Spec. Version 4.00 or higher [42:42]
|
||||
UINT32 ExSecurity:4; // Extended Security Support [46:43]
|
||||
UINT32 SdSpec3:1; // Spec. Version 3.00 or higher [47:47]
|
||||
UINT32 SdBusWidths:4; // DAT Bus widths supported [51:48]
|
||||
UINT32 SdSecurity:3; // CPRM security support [54:52]
|
||||
UINT32 DataStatAfterErase:1; // Data status after erases [55]
|
||||
UINT32 SdSpec:4; // SD Memory Card Spec. Version [59:56]
|
||||
UINT32 ScrStructure:4; // SCR Structure [63:60]
|
||||
} SD_SCR;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue