mirror of https://github.com/acidanthera/audk.git
QuarkPlatformPkg/PlatformFlashAccessLib: Add instance for update.
Add PlatformFlashAccessLib for capsule update. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Kelly Steele <kelly.steele@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
This commit is contained in:
Jiewen Yao
parent
bb7c65bd03
commit
63b9a685ad
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/** @file
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Platform Flash Access library.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <Library/BaseLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/PcdLib.h>
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#include <Library/PlatformFlashAccessLib.h>
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#include <Library/UefiBootServicesTableLib.h>
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#include <Protocol/Spi.h>
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//
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// SPI default opcode slots
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//
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#define SPI_OPCODE_JEDEC_ID_INDEX 0
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#define SPI_OPCODE_READ_ID_INDEX 1
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#define SPI_OPCODE_WRITE_S_INDEX 2
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#define SPI_OPCODE_WRITE_INDEX 3
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#define SPI_OPCODE_READ_INDEX 4
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#define SPI_OPCODE_ERASE_INDEX 5
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#define SPI_OPCODE_READ_S_INDEX 6
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#define SPI_OPCODE_CHIP_ERASE_INDEX 7
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#define SPI_ERASE_SECTOR_SIZE SIZE_4KB //This is the chipset requirement
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STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress;
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EFI_SPI_PROTOCOL *mSpiProtocol;
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/**
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Writes specified number of bytes from the input buffer to the address
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@param[in] WriteAddress The flash address to be written.
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@param[in, out] NumBytes The number of bytes.
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@param[in] Buffer The data buffer to be written.
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@return The status of flash write.
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**/
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EFI_STATUS
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FlashFdWrite (
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IN UINTN WriteAddress,
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IN OUT UINTN *NumBytes,
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IN UINT8 *Buffer
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)
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{
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EFI_STATUS Status;
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Status = EFI_SUCCESS;
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Status = mSpiProtocol->Execute (
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mSpiProtocol,
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SPI_OPCODE_WRITE_INDEX, // OpcodeIndex
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0, // PrefixOpcodeIndex
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TRUE, // DataCycle
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TRUE, // Atomic
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TRUE, // ShiftOut
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WriteAddress, // Address
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(UINT32) (*NumBytes), // Data Number
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Buffer,
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EnumSpiRegionBios
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);
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DEBUG((DEBUG_INFO, "FlashFdWrite - 0x%x - %r\n", (UINTN)WriteAddress, Status));
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AsmWbinvd ();
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return Status;
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}
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/**
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Erase a certain block from address LbaWriteAddress
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@param[in] WriteAddress The flash address to be erased.
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@return The status of flash erase.
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**/
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EFI_STATUS
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FlashFdErase (
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IN UINTN WriteAddress
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)
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{
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EFI_STATUS Status;
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Status = mSpiProtocol->Execute (
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mSpiProtocol,
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SPI_OPCODE_ERASE_INDEX, // OpcodeIndex
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0, // PrefixOpcodeIndex
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FALSE, // DataCycle
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TRUE, // Atomic
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FALSE, // ShiftOut
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WriteAddress, // Address
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0, // Data Number
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NULL,
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EnumSpiRegionBios // SPI_REGION_TYPE
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);
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DEBUG((DEBUG_INFO, "FlashFdErase - 0x%x - %r\n", (UINTN)WriteAddress, Status));
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AsmWbinvd ();
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return Status;
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}
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/**
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Perform flash write opreation.
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@param[in] FirmwareType The type of firmware.
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@param[in] FlashAddress The address of flash device to be accessed.
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@param[in] FlashAddressType The type of flash device address.
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@param[in] Buffer The pointer to the data buffer.
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@param[in] Length The length of data buffer in bytes.
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@retval EFI_SUCCESS The operation returns successfully.
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@retval EFI_WRITE_PROTECTED The flash device is read only.
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@retval EFI_UNSUPPORTED The flash device access is unsupported.
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@retval EFI_INVALID_PARAMETER The input parameter is not valid.
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**/
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EFI_STATUS
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EFIAPI
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PerformFlashWrite (
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IN PLATFORM_FIRMWARE_TYPE FirmwareType,
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IN EFI_PHYSICAL_ADDRESS FlashAddress,
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IN FLASH_ADDRESS_TYPE FlashAddressType,
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IN VOID *Buffer,
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IN UINTN Length
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)
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{
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EFI_STATUS Status;
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UINTN SectorNum;
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UINTN Index;
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UINTN NumBytes;
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DEBUG((DEBUG_INFO, "PerformFlashWrite - 0x%x(%x) - 0x%x\n", (UINTN)FlashAddress, (UINTN)FlashAddressType, Length));
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if (FlashAddressType == FlashAddressTypeAbsoluteAddress) {
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FlashAddress = FlashAddress - mInternalFdAddress;
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}
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//
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// Erase & Write
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//
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SectorNum = Length / SPI_ERASE_SECTOR_SIZE;
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for (Index = 0; Index < SectorNum; Index++){
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if (CompareMem(
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(UINT8 *)(UINTN)(FlashAddress + mInternalFdAddress) + Index * SPI_ERASE_SECTOR_SIZE,
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(UINT8 *)Buffer + Index * SPI_ERASE_SECTOR_SIZE,
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SPI_ERASE_SECTOR_SIZE) == 0) {
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DEBUG((DEBUG_INFO, "Sector - 0x%x - skip\n", Index));
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continue;
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}
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DEBUG((DEBUG_INFO, "Sector - 0x%x - update...\n", Index));
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Status = FlashFdErase (
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(UINTN)FlashAddress + Index * SPI_ERASE_SECTOR_SIZE
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);
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if (Status != EFI_SUCCESS){
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break;
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}
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NumBytes = SPI_ERASE_SECTOR_SIZE;
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Status = FlashFdWrite (
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(UINTN)FlashAddress + Index * SPI_ERASE_SECTOR_SIZE,
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&NumBytes,
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(UINT8 *)Buffer + Index * SPI_ERASE_SECTOR_SIZE
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);
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if (Status != EFI_SUCCESS){
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break;
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}
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}
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return EFI_SUCCESS;
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}
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/**
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Platform Flash Access Lib Constructor.
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@param[in] ImageHandle The firmware allocated handle for the EFI image.
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@param[in] SystemTable A pointer to the EFI System Table.
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@retval EFI_SUCCESS Constructor returns successfully.
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**/
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EFI_STATUS
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EFIAPI
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PerformFlashAccessLibConstructor (
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IN EFI_HANDLE ImageHandle,
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IN EFI_SYSTEM_TABLE *SystemTable
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)
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{
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EFI_STATUS Status;
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mInternalFdAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32(PcdFlashAreaBaseAddress);
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DEBUG((DEBUG_INFO, "PcdFlashAreaBaseAddress - 0x%x\n", mInternalFdAddress));
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Status = gBS->LocateProtocol(&gEfiSpiProtocolGuid, NULL, (VOID **)&mSpiProtocol);
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ASSERT_EFI_ERROR(Status);
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return EFI_SUCCESS;
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}
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@ -0,0 +1,53 @@
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## @file
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# Platform Flash Access library.
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#
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# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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##
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = PlatformFlashAccessLibDxe
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FILE_GUID = 9168384A-5F66-4CF7-AEB6-845BDEBD3012
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MODULE_TYPE = DXE_DRIVER
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VERSION_STRING = 1.0
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LIBRARY_CLASS = PlatformFlashAccessLib|DXE_DRIVER DXE_RUNTIME_DRIVER
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CONSTRUCTOR = PerformFlashAccessLibConstructor
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#
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# The following information is for reference only and not required by the build tools.
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#
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# VALID_ARCHITECTURES = IA32 X64 IPF EBC
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#
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[Sources]
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PlatformFlashAccessLibDxe.c
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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SignedCapsulePkg/SignedCapsulePkg.dec
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QuarkSocPkg/QuarkSocPkg.dec
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QuarkPlatformPkg/QuarkPlatformPkg.dec
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[LibraryClasses]
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BaseMemoryLib
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PcdLib
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DebugLib
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UefiBootServicesTableLib
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[Protocols]
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gEfiSpiProtocolGuid
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[Pcd]
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gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress
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[Depex]
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gEfiSpiProtocolGuid
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@ -0,0 +1,336 @@
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/** @file
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SPI flash device description.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include "SpiFlashDevice.h"
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#define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize))
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SPI_INIT_TABLE mSpiInitTable[] = {
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//
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// Macronix 32Mbit part
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//
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{
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SPI_MX25L3205_ID1,
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SPI_MX25L3205_ID2,
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SPI_MX25L3205_ID3,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
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},
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(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Winbond 32Mbit part
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//
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{
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SPI_W25X32_ID1,
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SF_DEVICE_ID0_W25QXX,
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SF_DEVICE_ID1_W25Q32,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
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},
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(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Winbond 32Mbit part
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//
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{
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SPI_W25X32_ID1,
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SPI_W25X32_ID2,
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SPI_W25X32_ID3,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
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},
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(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Atmel 32Mbit part
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//
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{
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SPI_AT26DF321_ID1,
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SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel
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SPI_AT26DF321_ID3,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
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},
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(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// Intel 32Mbit part bottom boot
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//
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{
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SPI_QH25F320_ID1,
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SPI_QH25F320_ID2,
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SPI_QH25F320_ID3,
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_ENABLE
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
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{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
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},
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0, // BIOS Start Offset
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FLASH_SIZE // BIOS image size in flash
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},
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//
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// SST 64Mbit part
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//
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{
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SPI_SST25VF080B_ID1, // VendorId
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SF_DEVICE_ID0_25VF064C, // DeviceId 0
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SF_DEVICE_ID1_25VF064C, // DeviceId 1
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{
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SPI_COMMAND_WRITE_ENABLE,
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SPI_COMMAND_WRITE_S_EN
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},
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{
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{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
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{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
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{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
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{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
|
||||
},
|
||||
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||||
FLASH_SIZE // BIOS image size in flash
|
||||
},
|
||||
//
|
||||
// NUMONYX 64Mbit part
|
||||
//
|
||||
{
|
||||
SF_VENDOR_ID_NUMONYX, // VendorId
|
||||
SF_DEVICE_ID0_M25PX64, // DeviceId 0
|
||||
SF_DEVICE_ID1_M25PX64, // DeviceId 1
|
||||
{
|
||||
SPI_COMMAND_WRITE_ENABLE,
|
||||
SPI_COMMAND_WRITE_S_EN
|
||||
},
|
||||
{
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
|
||||
},
|
||||
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||||
FLASH_SIZE // BIOS image size in flash
|
||||
},
|
||||
//
|
||||
// Atmel 64Mbit part
|
||||
//
|
||||
{
|
||||
SF_VENDOR_ID_ATMEL, // VendorId
|
||||
SF_DEVICE_ID0_AT25DF641, // DeviceId 0
|
||||
SF_DEVICE_ID1_AT25DF641, // DeviceId 1
|
||||
{
|
||||
SPI_COMMAND_WRITE_ENABLE,
|
||||
SPI_COMMAND_WRITE_S_EN
|
||||
},
|
||||
{
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
|
||||
},
|
||||
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||||
FLASH_SIZE // BIOS image size in flash
|
||||
},
|
||||
|
||||
//
|
||||
// Spansion 64Mbit part
|
||||
//
|
||||
{
|
||||
SF_VENDOR_ID_SPANSION, // VendorId
|
||||
SF_DEVICE_ID0_S25FL064K, // DeviceId 0
|
||||
SF_DEVICE_ID1_S25FL064K, // DeviceId 1
|
||||
{
|
||||
SPI_COMMAND_WRITE_ENABLE,
|
||||
SPI_COMMAND_WRITE_S_EN
|
||||
},
|
||||
{
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
|
||||
},
|
||||
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||||
FLASH_SIZE // BIOS image size in flash
|
||||
},
|
||||
|
||||
//
|
||||
// Macronix 64Mbit part bottom boot
|
||||
//
|
||||
{
|
||||
SF_VENDOR_ID_MX, // VendorId
|
||||
SF_DEVICE_ID0_25L6405D, // DeviceId 0
|
||||
SF_DEVICE_ID1_25L6405D, // DeviceId 1
|
||||
{
|
||||
SPI_COMMAND_WRITE_ENABLE,
|
||||
SPI_COMMAND_WRITE_S_EN
|
||||
},
|
||||
{
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
|
||||
},
|
||||
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||||
FLASH_SIZE // BIOS image size in flash
|
||||
},
|
||||
//
|
||||
// Winbond 64Mbit part bottom boot
|
||||
//
|
||||
{
|
||||
SPI_W25X64_ID1,
|
||||
SF_DEVICE_ID0_W25QXX,
|
||||
SF_DEVICE_ID1_W25Q64,
|
||||
{
|
||||
SPI_COMMAND_WRITE_ENABLE,
|
||||
SPI_COMMAND_WRITE_S_EN
|
||||
},
|
||||
{
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
|
||||
},
|
||||
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||||
FLASH_SIZE // BIOS image size in flash
|
||||
},
|
||||
//
|
||||
// Winbond 64Mbit part bottom boot
|
||||
//
|
||||
{
|
||||
SPI_W25X64_ID1,
|
||||
SPI_W25X64_ID2,
|
||||
SPI_W25X64_ID3,
|
||||
{
|
||||
SPI_COMMAND_WRITE_ENABLE,
|
||||
SPI_COMMAND_WRITE_S_EN
|
||||
},
|
||||
{
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}
|
||||
},
|
||||
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||||
FLASH_SIZE // BIOS image size in flash
|
||||
},
|
||||
//
|
||||
// Intel 64Mbit part bottom boot
|
||||
//
|
||||
{
|
||||
SPI_QH25F640_ID1,
|
||||
SPI_QH25F640_ID2,
|
||||
SPI_QH25F640_ID3,
|
||||
{
|
||||
SPI_COMMAND_WRITE_ENABLE,
|
||||
SPI_COMMAND_WRITE_S_EN
|
||||
},
|
||||
{
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},
|
||||
{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},
|
||||
{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},
|
||||
{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},
|
||||
{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}
|
||||
},
|
||||
0x800000 - FLASH_SIZE, // BIOS Start Offset
|
||||
FLASH_SIZE // BIOS image size in flash
|
||||
}
|
||||
};
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
/** @file
|
||||
SPI flash device header file.
|
||||
|
||||
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php
|
||||
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
**/
|
||||
|
||||
#ifndef _SPI_FLASH_DEVICE_H_
|
||||
#define _SPI_FLASH_DEVICE_H_
|
||||
|
||||
#include <PiDxe.h>
|
||||
#include <Protocol/Spi.h>
|
||||
#include <Protocol/FirmwareVolumeBlock.h>
|
||||
|
||||
//
|
||||
// Supported SPI Flash Devices
|
||||
//
|
||||
typedef enum {
|
||||
EnumSpiFlash25L3205D, // Macronix 32Mbit part
|
||||
EnumSpiFlashW25Q32, // Winbond 32Mbit part
|
||||
EnumSpiFlashW25X32, // Winbond 32Mbit part
|
||||
EnumSpiFlashAT25DF321, // Atmel 32Mbit part
|
||||
EnumSpiFlashQH25F320, // Intel 32Mbit part
|
||||
EnumSpiFlash25VF064C, // SST 64Mbit part
|
||||
EnumSpiFlashM25PX64, // NUMONYX 64Mbit part
|
||||
EnumSpiFlashAT25DF641, // Atmel 64Mbit part
|
||||
EnumSpiFlashS25FL064K, // Spansion 64Mbit part
|
||||
EnumSpiFlash25L6405D, // Macronix 64Mbit part
|
||||
EnumSpiFlashW25Q64, // Winbond 64Mbit part
|
||||
EnumSpiFlashW25X64, // Winbond 64Mbit part
|
||||
EnumSpiFlashQH25F640, // Intel 64Mbit part
|
||||
EnumSpiFlashMax
|
||||
} SPI_FLASH_TYPES_SUPPORTED;
|
||||
|
||||
//
|
||||
// Flash Device commands
|
||||
//
|
||||
// If a supported device uses a command different from the list below, a device specific command
|
||||
// will be defined just below it's JEDEC id section.
|
||||
//
|
||||
#define SPI_COMMAND_WRITE 0x02
|
||||
#define SPI_COMMAND_WRITE_AAI 0xAD
|
||||
#define SPI_COMMAND_READ 0x03
|
||||
#define SPI_COMMAND_ERASE 0x20
|
||||
#define SPI_COMMAND_WRITE_DISABLE 0x04
|
||||
#define SPI_COMMAND_READ_S 0x05
|
||||
#define SPI_COMMAND_WRITE_ENABLE 0x06
|
||||
#define SPI_COMMAND_READ_ID 0xAB
|
||||
#define SPI_COMMAND_JEDEC_ID 0x9F
|
||||
#define SPI_COMMAND_WRITE_S_EN 0x50
|
||||
#define SPI_COMMAND_WRITE_S 0x01
|
||||
#define SPI_COMMAND_CHIP_ERASE 0xC7
|
||||
#define SPI_COMMAND_BLOCK_ERASE 0xD8
|
||||
|
||||
//
|
||||
// Flash JEDEC device ids
|
||||
//
|
||||
// SST 8Mbit part
|
||||
//
|
||||
#define SPI_SST25VF080B_ID1 0xBF
|
||||
#define SPI_SST25VF080B_ID2 0x25
|
||||
#define SPI_SST25VF080B_ID3 0x8E
|
||||
//
|
||||
// SST 16Mbit part
|
||||
//
|
||||
#define SPI_SST25VF016B_ID1 0xBF
|
||||
#define SPI_SST25VF016B_ID2 0x25
|
||||
#define SPI_SST25V016BF_ID3 0x41
|
||||
//
|
||||
// Macronix 32Mbit part
|
||||
//
|
||||
// MX25 part does not support WRITE_AAI comand (0xAD)
|
||||
//
|
||||
#define SPI_MX25L3205_ID1 0xC2
|
||||
#define SPI_MX25L3205_ID2 0x20
|
||||
#define SPI_MX25L3205_ID3 0x16
|
||||
//
|
||||
// Intel 32Mbit part bottom boot
|
||||
//
|
||||
#define SPI_QH25F320_ID1 0x89
|
||||
#define SPI_QH25F320_ID2 0x89
|
||||
#define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot
|
||||
//
|
||||
// Intel 64Mbit part bottom boot
|
||||
//
|
||||
#define SPI_QH25F640_ID1 0x89
|
||||
#define SPI_QH25F640_ID2 0x89
|
||||
#define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot
|
||||
//
|
||||
// QH part does not support command 0x20 for erase; only 0xD8 (sector erase)
|
||||
// QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)
|
||||
// 0x40 command ignored if address outside of parameter block range
|
||||
//
|
||||
#define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40
|
||||
//
|
||||
// Winbond 32Mbit part
|
||||
//
|
||||
#define SPI_W25X32_ID1 0xEF
|
||||
#define SPI_W25X32_ID2 0x30 // Memory Type
|
||||
#define SPI_W25X32_ID3 0x16 // Capacity
|
||||
#define SF_DEVICE_ID1_W25Q32 0x16
|
||||
|
||||
//
|
||||
// Winbond 64Mbit part
|
||||
//
|
||||
#define SPI_W25X64_ID1 0xEF
|
||||
#define SPI_W25X64_ID2 0x30 // Memory Type
|
||||
#define SPI_W25X64_ID3 0x17 // Capacity
|
||||
#define SF_DEVICE_ID0_W25QXX 0x40
|
||||
#define SF_DEVICE_ID1_W25Q64 0x17
|
||||
//
|
||||
// Winbond 128Mbit part
|
||||
//
|
||||
#define SF_DEVICE_ID0_W25Q128 0x40
|
||||
#define SF_DEVICE_ID1_W25Q128 0x18
|
||||
|
||||
//
|
||||
// Atmel 32Mbit part
|
||||
//
|
||||
#define SPI_AT26DF321_ID1 0x1F
|
||||
#define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density
|
||||
#define SPI_AT26DF321_ID3 0x00
|
||||
|
||||
#define SF_VENDOR_ID_ATMEL 0x1F
|
||||
#define SF_DEVICE_ID0_AT25DF641 0x48
|
||||
#define SF_DEVICE_ID1_AT25DF641 0x00
|
||||
|
||||
//
|
||||
// SST 8Mbit part
|
||||
//
|
||||
#define SPI_SST25VF080B_ID1 0xBF
|
||||
#define SPI_SST25VF080B_ID2 0x25
|
||||
#define SPI_SST25VF080B_ID3 0x8E
|
||||
#define SF_DEVICE_ID0_25VF064C 0x25
|
||||
#define SF_DEVICE_ID1_25VF064C 0x4B
|
||||
|
||||
//
|
||||
// SST 16Mbit part
|
||||
//
|
||||
#define SPI_SST25VF016B_ID1 0xBF
|
||||
#define SPI_SST25VF016B_ID2 0x25
|
||||
#define SPI_SST25V016BF_ID3 0x41
|
||||
|
||||
//
|
||||
// Winbond 32Mbit part
|
||||
//
|
||||
#define SPI_W25X32_ID1 0xEF
|
||||
#define SPI_W25X32_ID2 0x30 // Memory Type
|
||||
#define SPI_W25X32_ID3 0x16 // Capacity
|
||||
|
||||
#define SF_VENDOR_ID_MX 0xC2
|
||||
#define SF_DEVICE_ID0_25L6405D 0x20
|
||||
#define SF_DEVICE_ID1_25L6405D 0x17
|
||||
|
||||
#define SF_VENDOR_ID_NUMONYX 0x20
|
||||
#define SF_DEVICE_ID0_M25PX64 0x71
|
||||
#define SF_DEVICE_ID1_M25PX64 0x17
|
||||
|
||||
//
|
||||
// Spansion 64Mbit part
|
||||
//
|
||||
#define SF_VENDOR_ID_SPANSION 0xEF
|
||||
#define SF_DEVICE_ID0_S25FL064K 0x40
|
||||
#define SF_DEVICE_ID1_S25FL064K 0x00
|
||||
|
||||
//
|
||||
// index for prefix opcodes
|
||||
//
|
||||
#define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE
|
||||
#define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN
|
||||
#define BIOS_CTRL 0xDC
|
||||
|
||||
#define PFAB_CARD_DEVICE_ID 0x5150
|
||||
#define PFAB_CARD_VENDOR_ID 0x8086
|
||||
#define PFAB_CARD_SETUP_REGISTER 0x40
|
||||
#define PFAB_CARD_SETUP_BYTE 0x0d
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue