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Add ARM support 

Add C inline assembly files for IA32 and X64 GCC builds.


git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9113 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
mdkinney 2009-08-18 21:04:14 +00:00
parent 3c99107841
commit 64698eb841
18 changed files with 4491 additions and 2 deletions
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36
MdePkg/Library/BaseLib/Arm/CpuBreakpoint.S Normal file
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#------------------------------------------------------------------------------
#
# CpuBreakpoint() for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.align 2
.globl ASM_PFX(CpuBreakpoint)
#/**
# Generates a breakpoint on the CPU.
#
# Generates a breakpoint on the CPU. The breakpoint must be implemented such
# that code can resume normal execution after the breakpoint.
#
#**/
#VOID
#EFIAPI
#CpuBreakpoint (
# VOID
# );
#
ASM_PFX(CpuBreakpoint):
swi 0xdbdbdb
bx lr

38
MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm Normal file
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;------------------------------------------------------------------------------
;
; CpuBreakpoint() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT CpuBreakpoint
AREA Cpu_Breakpoint, CODE, READONLY
;/**
; Generates a breakpoint on the CPU.
;
; Generates a breakpoint on the CPU. The breakpoint must be implemented such
; that code can resume normal execution after the breakpoint.
;
;**/
;VOID
;EFIAPI
;CpuBreakpoint (
; VOID
; );
;
CpuBreakpoint
swi 0xdbdbdb
bx lr
END

41
MdePkg/Library/BaseLib/Arm/CpuPause.asm Normal file
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;------------------------------------------------------------------------------
;
; CpuPause() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT CpuPause
AREA cpu_pause, CODE, READONLY
;/**
; Requests CPU to pause for a short period of time.
;
; Requests CPU to pause for a short period of time. Typically used in MP
; systems to prevent memory starvation while waiting for a spin lock.
;
;**/
;VOID
;EFIAPI
;CpuPause (
; VOID
; );
;
CpuPause
NOP
NOP
NOP
NOP
NOP
BX LR
END

35
MdePkg/Library/BaseLib/Arm/DisableInterrupts.S Normal file
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#------------------------------------------------------------------------------
#
# DisableInterrupts() for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl ASM_PFX(DisableInterrupts)
#/**
# Disables CPU interrupts.
#
#**/
#VOID
#EFIAPI
#DisableInterrupts (
# VOID
# );
#
ASM_PFX(DisableInterrupts):
mrs R0,CPSR
orr R0,R0,#0x80 @Disable IRQ interrupts
msr CPSR_c,R0
bx LR

37
MdePkg/Library/BaseLib/Arm/DisableInterrupts.asm Normal file
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;------------------------------------------------------------------------------
;
; DisableInterrupts() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT DisableInterrupts
AREA Interrupt_disable, CODE, READONLY
;/**
; Disables CPU interrupts.
;
;**/
;VOID
;EFIAPI
;DisableInterrupts (
; VOID
; );
;
DisableInterrupts
MRS R0,CPSR
ORR R0,R0,#0x80 ;Disable IRQ interrupts
MSR CPSR_c,R0
BX LR
END

36
MdePkg/Library/BaseLib/Arm/EnableInterrupts.S Normal file
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#------------------------------------------------------------------------------
#
# EnableInterrupts() for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl ASM_PFX(EnableInterrupts)
#/**
# Enables CPU interrupts.
#
#**/
#VOID
#EFIAPI
#EnableInterrupts (
# VOID
# );
#
ASM_PFX(EnableInterrupts):
mrs R0,CPSR
bic R0,R0,#0x80 @Enable IRQ interrupts
msr CPSR_c,R0
bx LR

37
MdePkg/Library/BaseLib/Arm/EnableInterrupts.asm Normal file
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;------------------------------------------------------------------------------
;
; EnableInterrupts() for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT EnableInterrupts
AREA Interrupt_enable, CODE, READONLY
;/**
; Enables CPU interrupts.
;
;**/
;VOID
;EFIAPI
;EnableInterrupts (
; VOID
; );
;
EnableInterrupts
MRS R0,CPSR
BIC R0,R0,#0x80 ;Enable IRQ interrupts
MSR CPSR_c,R0
BX LR
END

61
MdePkg/Library/BaseLib/Arm/GccInline.c Normal file
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/** @file
GCC inline implementation of BaseLib processor specific functions.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Requests CPU to pause for a short period of time.
Requests CPU to pause for a short period of time. Typically used in MP
systems to prevent memory starvation while waiting for a spin lock.
**/
VOID
EFIAPI
CpuPause (
VOID
)
{
__asm__ __volatile__ (
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
);
}
VOID
EFIAPI
InternalSwitchStackAsm (
SWITCH_STACK_ENTRY_POINT EntryPoint,
VOID *Context,
VOID *Context2,
VOID *NewStack
)
{
__asm__ __volatile__ (
"mov lr, %0\n\t"
"mov sp, %3\n\t"
"mov %r0, %1\n\t"
"mov %r1, %2\n\t"
"bx lr\n\t"
: /* no output operand */
: "r" (EntryPoint),
"r" (Context),
"r" (Context2),
"r" (NewStack)
);
}

43
MdePkg/Library/BaseLib/Arm/GetInterruptsState.S Normal file
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#------------------------------------------------------------------------------
#
# GetInterruptState() function for ARM
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl _GetInterruptState
#/**
# Retrieves the current CPU interrupt state.
#
# Returns TRUE is interrupts are currently enabled. Otherwise
# returns FALSE.
#
# @retval TRUE CPU interrupts are enabled.
# @retval FALSE CPU interrupts are disabled.
#
#**/
#
#BOOLEAN
#EFIAPI
#GetInterruptState (
# VOID
# );
#
_GetInterruptState:
mrs R0, CPSR
tst R0, #0x80 @Check if IRQ is enabled.
moveq R0, #1
movne R0, #0
bx LR

45
MdePkg/Library/BaseLib/Arm/GetInterruptsState.asm Normal file
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;------------------------------------------------------------------------------
;
; GetInterruptState() function for ARM
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT GetInterruptState
AREA Interrupt_enable, CODE, READONLY
;/**
; Retrieves the current CPU interrupt state.
;
; Returns TRUE is interrupts are currently enabled. Otherwise
; returns FALSE.
;
; @retval TRUE CPU interrupts are enabled.
; @retval FALSE CPU interrupts are disabled.
;
;**/
;
;BOOLEAN
;EFIAPI
;GetInterruptState (
; VOID
; );
;
GetInterruptState
MRS R0, CPSR
TST R0, #0x80 ;Check if IRQ is enabled.
MOVEQ R0, #1
MOVNE R0, #0
BX LR
END

59
MdePkg/Library/BaseLib/Arm/InternalSwitchStack.c Normal file
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/** @file
SwitchStack() function for ARM.
Copyright (c) 2006 - 2007, Intel Corporation<BR>
Portions copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Transfers control to a function starting with a new stack.
Transfers control to the function specified by EntryPoint using the
new stack specified by NewStack and passing in the parameters specified
by Context1 and Context2. Context1 and Context2 are optional and may
be NULL. The function EntryPoint must never return.
Marker will be ignored on IA-32, x64, and EBC.
IPF CPUs expect one additional parameter of type VOID * that specifies
the new backing store pointer.
If EntryPoint is NULL, then ASSERT().
If NewStack is NULL, then ASSERT().
@param EntryPoint A pointer to function to call with the new stack.
@param Context1 A pointer to the context to pass into the EntryPoint
function.
@param Context2 A pointer to the context to pass into the EntryPoint
function.
@param NewStack A pointer to the new stack to use for the EntryPoint
function.
@param Marker VA_LIST marker for the variable argument list.
**/
VOID
EFIAPI
InternalSwitchStack (
IN SWITCH_STACK_ENTRY_POINT EntryPoint,
IN VOID *Context1, OPTIONAL
IN VOID *Context2, OPTIONAL
IN VOID *NewStack,
IN VA_LIST Marker
)
{
//
// Stack should be aligned with CPU_STACK_ALIGNMENT
//
ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);
InternalSwitchStackAsm (EntryPoint, Context1, Context2, NewStack);
}

70
MdePkg/Library/BaseLib/Arm/SetJumpLongJump.S Normal file
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#------------------------------------------------------------------------------
#
# Copyright (c) 2006 - 2009, Intel Corporation<BR>
# Portions copyright (c) 2008-2009 Apple Inc.<BR>
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
.text
.p2align 2
.globl ASM_PFX(SetJump)
.globl ASM_PFX(InternalLongJump)
#/**
# Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
#
# Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
# call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
# value to be returned by SetJump().
#
# If JumpBuffer is NULL, then ASSERT().
# For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
#
# @param JumpBuffer A pointer to CPU context buffer.
#
#**/
#
#UINTN
#EFIAPI
#SetJump (
# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
# );
#
ASM_PFX(SetJump):
mov r3, r13
stmia r0, {r3-r12,r14}
eor r0, r0, r0
bx lr
#/**
# Restores the CPU context that was saved with SetJump().#
#
# Restores the CPU context from the buffer specified by JumpBuffer.
# This function never returns to the caller.
# Instead is resumes execution based on the state of JumpBuffer.
#
# @param JumpBuffer A pointer to CPU context buffer.
# @param Value The value to return when the SetJump() context is restored.
#
#**/
#VOID
#EFIAPI
#InternalLongJump (
# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
# IN UINTN Value // R1
# );
#
ASM_PFX(InternalLongJump):
ldmia r0, {r3-r12,r14}
mov r13, r3
mov r0, r1
bx lr
ASM_FUNCTION_REMOVE_IF_UNREFERENCED()

70
MdePkg/Library/BaseLib/Arm/SetJumpLongJump.asm Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT SetJump
EXPORT InternalLongJump
AREA BaseLib, CODE, READONLY
;/**
; Saves the current CPU context that can be restored with a call to LongJump() and returns 0.;
;
; Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
; call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
; value to be returned by SetJump().
;
; If JumpBuffer is NULL, then ASSERT().
; For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
;
; @param JumpBuffer A pointer to CPU context buffer.
;
;**/
;
;UINTN
;EFIAPI
;SetJump (
; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // R0
; )
;
SetJump
MOV R3, R13
STM R0, {R3-R12,R14}
EOR R0, R0
BX LR
;/**
; Restores the CPU context that was saved with SetJump().;
;
; Restores the CPU context from the buffer specified by JumpBuffer.
; This function never returns to the caller.
; Instead is resumes execution based on the state of JumpBuffer.
;
; @param JumpBuffer A pointer to CPU context buffer.
; @param Value The value to return when the SetJump() context is restored.
;
;**/
;VOID
;EFIAPI
;InternalLongJump (
; IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // R0
; IN UINTN Value // R1
; );
;
InternalLongJump
LDM R0, {R3-R12,R14}
MOV R13, R3
MOV R0, R1
BX LR
END

45
MdePkg/Library/BaseLib/Arm/SwitchStack.asm Normal file
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;------------------------------------------------------------------------------
;
; Copyright (c) 2006 - 2009, Intel Corporation<BR>
; Portions copyright (c) 2008-2009 Apple Inc.<BR>
; All rights reserved. This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
; http://opensource.org/licenses/bsd-license.php
;
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
;
;------------------------------------------------------------------------------
EXPORT InternalSwitchStackAsm
AREA Switch_Stack, CODE, READONLY
;/**
; This allows the caller to switch the stack and goes to the new entry point
;
; @param EntryPoint Pointer to the location to enter
; @param Context Parameter to pass in
; @param Context2 Parameter2 to pass in
; @param NewStack New Location of the stack
;
; @return Nothing. Goes to the Entry Point passing in the new parameters
;
;**/
;VOID
;EFIAPI
;InternalSwitchStackAsm (
; SWITCH_STACK_ENTRY_POINT EntryPoint,
; VOID *Context,
; VOID *Context2,
; VOID *NewStack
; );
;
InternalSwitchStackAsm
MOV LR, R0
MOV SP, R3
MOV R0, R1
MOV R1, R2
BX LR
END

252
MdePkg/Library/BaseLib/Arm/Unaligned.c Normal file
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/** @file
Unaligned access functions of BaseLib for ARM.
volatile was added to work around optimization issues.
Copyright (c) 2006 - 2009, Intel Corporation<BR>
Portions Copyright (c) 2008-2009 Apple Inc.<BR>
All rights reserved. This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include "BaseLibInternals.h"
/**
Reads a 16-bit value from memory that may be unaligned.
This function returns the 16-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@return The 16-bit value read from Buffer.
**/
UINT16
EFIAPI
ReadUnaligned16 (
IN CONST UINT16 *Buffer
)
{
volatile UINT8 LowerByte;
volatile UINT8 HigherByte;
ASSERT (Buffer != NULL);
LowerByte = ((UINT8*)Buffer)[0];
HigherByte = ((UINT8*)Buffer)[1];
return (UINT16)(LowerByte | (HigherByte << 8));
}
/**
Writes a 16-bit value to memory that may be unaligned.
This function writes the 16-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 16-bit value that may be unaligned.
@param Value 16-bit value to write to Buffer.
@return The 16-bit value to write to Buffer.
**/
UINT16
EFIAPI
WriteUnaligned16 (
OUT UINT16 *Buffer,
IN UINT16 Value
)
{
ASSERT (Buffer != NULL);
((volatile UINT8*)Buffer)[0] = (UINT8)Value;
((volatile UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
return Value;
}
/**
Reads a 24-bit value from memory that may be unaligned.
This function returns the 24-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@return The 24-bit value read from Buffer.
**/
UINT32
EFIAPI
ReadUnaligned24 (
IN CONST UINT32 *Buffer
)
{
ASSERT (Buffer != NULL);
return (UINT32)(
ReadUnaligned16 ((UINT16*)Buffer) |
(((UINT8*)Buffer)[2] << 16)
);
}
/**
Writes a 24-bit value to memory that may be unaligned.
This function writes the 24-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 24-bit value that may be unaligned.
@param Value 24-bit value to write to Buffer.
@return The 24-bit value to write to Buffer.
**/
UINT32
EFIAPI
WriteUnaligned24 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
*(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
return Value;
}
/**
Reads a 32-bit value from memory that may be unaligned.
This function returns the 32-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@return The 32-bit value read from Buffer.
**/
UINT32
EFIAPI
ReadUnaligned32 (
IN CONST UINT32 *Buffer
)
{
UINT16 LowerBytes;
UINT16 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
return (UINT32) (LowerBytes | (HigherBytes << 16));
}
/**
Writes a 32-bit value to memory that may be unaligned.
This function writes the 32-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 32-bit value that may be unaligned.
@param Value 32-bit value to write to Buffer.
@return The 32-bit value to write to Buffer.
**/
UINT32
EFIAPI
WriteUnaligned32 (
OUT UINT32 *Buffer,
IN UINT32 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
return Value;
}
/**
Reads a 64-bit value from memory that may be unaligned.
This function returns the 64-bit value pointed to by Buffer. The function
guarantees that the read operation does not produce an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@return The 64-bit value read from Buffer.
**/
UINT64
EFIAPI
ReadUnaligned64 (
IN CONST UINT64 *Buffer
)
{
UINT32 LowerBytes;
UINT32 HigherBytes;
ASSERT (Buffer != NULL);
LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
}
/**
Writes a 64-bit value to memory that may be unaligned.
This function writes the 64-bit value specified by Value to Buffer. Value is
returned. The function guarantees that the write operation does not produce
an alignment fault.
If the Buffer is NULL, then ASSERT().
@param Buffer Pointer to a 64-bit value that may be unaligned.
@param Value 64-bit value to write to Buffer.
@return The 64-bit value to write to Buffer.
**/
UINT64
EFIAPI
WriteUnaligned64 (
OUT UINT64 *Buffer,
IN UINT64 Value
)
{
ASSERT (Buffer != NULL);
WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
return Value;
}

24
MdePkg/Library/BaseLib/BaseLib.inf
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@ -1,7 +1,8 @@
#/** @file
# Base Library implementation.
#
# Copyright (c) 2007 - 2009, Intel Corporation.
# Copyright (c) 2007 - 2009, Intel Corporation.<BR>
# Portions Copyright (c) 2008-2009 Apple Inc.<BR>
#
# All rights reserved. This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -22,7 +23,7 @@
LIBRARY_CLASS = BaseLib
#
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM
#
[Sources.common]
@ -583,6 +584,25 @@
Unaligned.c
Math64.c
[Sources.ARM]
Arm/InternalSwitchStack.c
Arm/Unaligned.c
Math64.c
Arm/SwitchStack.asm | RVCT
Arm/SetJumpLongJump.asm | RVCT
Arm/DisableInterrupts.asm | RVCT
Arm/EnableInterrupts.asm | RVCT
Arm/GetInterruptsState.asm | RVCT
Arm/CpuPause.asm | RVCT
Arm/CpuBreakpoint.asm
Arm/GccInline.c | GCC
Arm/EnableInterrupts.S | GCC
Arm/DisableInterrupts.S | GCC
Arm/SetJumpLongJump.S | GCC
Arm/CpuBreakpoint.S | GCC
[Packages]
MdePkg/MdePkg.dec

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MdePkg/Library/BaseLib/Ia32/GccInline.c Normal file
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1806
MdePkg/Library/BaseLib/X64/GccInline.c Normal file
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