tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

MdeModulePkg/NvmExpress: Clean Phase/CqHdbl/SqTdbl fields to restart HC 

Phase Tag, SqTdbl/CqHdbl and SqBuffer/CqBuffer should be cleared in
NvmeControllerInit() to make HC functionality work when user invokes
NvmeBlockIoReset().

Cc: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com>
This commit is contained in:
Tian Feng 2015-11-24 16:45:44 +08:00 committed by Feng Tian
parent da7c72740f
commit 6523ae8baa
2 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpress.c
View File

@ -770,7 +770,6 @@ NvmExpressDriverBindingStart (
} }
Private->BufferPciAddr = (UINT8 *)(UINTN)MappedAddr; Private->BufferPciAddr = (UINT8 *)(UINTN)MappedAddr;
ZeroMem (Private->Buffer, EFI_PAGES_TO_SIZE (4));
Private->Signature = NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE; Private->Signature = NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE;
Private->ControllerHandle = Controller; Private->ControllerHandle = Controller;

9
MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressHci.c
View File

@ -844,6 +844,12 @@ NvmeControllerInit (
Private->Cid[0] = 0; Private->Cid[0] = 0;
Private->Cid[1] = 0; Private->Cid[1] = 0;
Private->Pt[0] = 0;
Private->Pt[1] = 0;
Private->SqTdbl[0].Sqt = 0;
Private->SqTdbl[1].Sqt = 0;
Private->CqHdbl[0].Cqh = 0;
Private->CqHdbl[1].Cqh = 0;
Status = NvmeDisableController (Private); Status = NvmeDisableController (Private);
@ -872,6 +878,7 @@ NvmeControllerInit (
// //
// Address of I/O submission & completion queue. // Address of I/O submission & completion queue.
// //
ZeroMem (Private->Buffer, EFI_PAGES_TO_SIZE (4));
Private->SqBuffer[0] = (NVME_SQ *)(UINTN)(Private->Buffer); Private->SqBuffer[0] = (NVME_SQ *)(UINTN)(Private->Buffer);
Private->SqBufferPciAddr[0] = (NVME_SQ *)(UINTN)(Private->BufferPciAddr); Private->SqBufferPciAddr[0] = (NVME_SQ *)(UINTN)(Private->BufferPciAddr);
Private->CqBuffer[0] = (NVME_CQ *)(UINTN)(Private->Buffer + 1 * EFI_PAGE_SIZE); Private->CqBuffer[0] = (NVME_CQ *)(UINTN)(Private->Buffer + 1 * EFI_PAGE_SIZE);
@ -924,11 +931,13 @@ NvmeControllerInit (
// //
// Allocate buffer for Identify Controller data // Allocate buffer for Identify Controller data
// //
if (Private->ControllerData == NULL) {
Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof(NVME_ADMIN_CONTROLLER_DATA)); Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof(NVME_ADMIN_CONTROLLER_DATA));
if (Private->ControllerData == NULL) { if (Private->ControllerData == NULL) {
return EFI_OUT_OF_RESOURCES; return EFI_OUT_OF_RESOURCES;
} }
}
// //
// Get current Identify Controller Data // Get current Identify Controller Data