mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/NvmExpress: Clean Phase/CqHdbl/SqTdbl fields to restart HC
Phase Tag, SqTdbl/CqHdbl and SqBuffer/CqBuffer should be cleared in NvmeControllerInit() to make HC functionality work when user invokes NvmeBlockIoReset(). Cc: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Simon (Xiang) Lian-SSI <simon.lian@ssi.samsung.com>
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@ -770,7 +770,6 @@ NvmExpressDriverBindingStart (
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}
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Private->BufferPciAddr = (UINT8 *)(UINTN)MappedAddr;
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ZeroMem (Private->Buffer, EFI_PAGES_TO_SIZE (4));
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Private->Signature = NVME_CONTROLLER_PRIVATE_DATA_SIGNATURE;
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Private->ControllerHandle = Controller;
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@ -844,6 +844,12 @@ NvmeControllerInit (
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Private->Cid[0] = 0;
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Private->Cid[1] = 0;
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Private->Pt[0] = 0;
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Private->Pt[1] = 0;
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Private->SqTdbl[0].Sqt = 0;
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Private->SqTdbl[1].Sqt = 0;
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Private->CqHdbl[0].Cqh = 0;
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Private->CqHdbl[1].Cqh = 0;
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Status = NvmeDisableController (Private);
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@ -872,6 +878,7 @@ NvmeControllerInit (
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//
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// Address of I/O submission & completion queue.
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//
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ZeroMem (Private->Buffer, EFI_PAGES_TO_SIZE (4));
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Private->SqBuffer[0] = (NVME_SQ *)(UINTN)(Private->Buffer);
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Private->SqBufferPciAddr[0] = (NVME_SQ *)(UINTN)(Private->BufferPciAddr);
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Private->CqBuffer[0] = (NVME_CQ *)(UINTN)(Private->Buffer + 1 * EFI_PAGE_SIZE);
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@ -924,11 +931,13 @@ NvmeControllerInit (
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//
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// Allocate buffer for Identify Controller data
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//
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if (Private->ControllerData == NULL) {
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Private->ControllerData = (NVME_ADMIN_CONTROLLER_DATA *)AllocateZeroPool (sizeof(NVME_ADMIN_CONTROLLER_DATA));
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if (Private->ControllerData == NULL) {
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return EFI_OUT_OF_RESOURCES;
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}
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}
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//
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// Get current Identify Controller Data
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