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Fix bug in UncachedMemoryAllocationLib, Assembler, make DefaultExceptionHandler lib inc the PC past the faulting instruction to aid debug. Update LR in Exception hanlder, so return address can get updated properly. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10018 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-02-16 23:45:42 +00:00
parent 56015d8801
commit 65e2744587
5 changed files with 13 additions and 8 deletions
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1
ArmPkg/Drivers/CpuDxe/ExceptionSupport.ARMv6.asm
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@ -229,6 +229,7 @@ AsmCommonExceptionEntry
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry
addne R5, R5, #2 ; PC += 2; addne R5, R5, #2 ; PC += 2;
str R5,[SP,#0x58] ; Update LR value pused by srsfd
NoAdjustNeeded NoAdjustNeeded

7
ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c
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@ -339,7 +339,7 @@ THUMB_INSTRUCTIONS gOpThumb2[] = {
{ "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]} { "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}
{ "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]} { "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}
{ "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} { "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}
{ "LDRSB", 0xf9900800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form? { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?
{ "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form? { "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?
{ "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]} { "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}
{ "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]} { "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}
@ -791,7 +791,6 @@ DisassembleThumbInstruction (
return; return;
case LDM_REG_IMM8: case LDM_REG_IMM8:
ASSERT (FALSE);
// <rt>, [<rn>, {, #<imm8>}]{!} // <rt>, [<rn>, {, #<imm8>}]{!}
W = (OpCode32 & BIT8) == BIT8; W = (OpCode32 & BIT8) == BIT8;
U = (OpCode32 & BIT9) == BIT9; U = (OpCode32 & BIT9) == BIT9;
@ -801,10 +800,10 @@ DisassembleThumbInstruction (
if ((OpCode32 && 0xff) == 0) { if ((OpCode32 && 0xff) == 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":""); AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", W?"!":"");
} else { } else {
AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", OpCode32 & 0xff, U?"":"-" , W?"!":""); AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", U?"":"-" , OpCode32 & 0xff, W?"!":"");
} }
} else { } else {
AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x]", OpCode32 & 0xff, U?"":"-"); AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", U?"":"-", OpCode32 & 0xff);
} }
return; return;

7
ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandler.c
View File

@ -224,6 +224,7 @@ DefaultExceptionHandler (
) )
{ {
UINT32 DfsrStatus; UINT32 DfsrStatus;
UINT32 IfsrStatus;
BOOLEAN DfsrWrite; BOOLEAN DfsrWrite;
UINT32 PcAdjust = 0; UINT32 PcAdjust = 0;
@ -289,8 +290,10 @@ DefaultExceptionHandler (
if (DfsrStatus != 0x00) { if (DfsrStatus != 0x00) {
DEBUG ((EFI_D_ERROR, " %a: %a 0x%08x\n", FaultStatusToString (DfsrStatus), DfsrWrite ? "write to" : "read from", SystemContext.SystemContextArm->DFAR)); DEBUG ((EFI_D_ERROR, " %a: %a 0x%08x\n", FaultStatusToString (DfsrStatus), DfsrWrite ? "write to" : "read from", SystemContext.SystemContextArm->DFAR));
} }
if ((SystemContext.SystemContextArm->IFSR & 0xf) != 0x00) {
DEBUG ((EFI_D_ERROR, "Instruction %a at 0x%08x, \n", FaultStatusToString (SystemContext.SystemContextArm->IFSR & 0xf), SystemContext.SystemContextArm->IFAR)); IfsrStatus = (SystemContext.SystemContextArm->IFSR & 0xf) | ((SystemContext.SystemContextArm->IFSR >> 6) & 0x10);
if (IfsrStatus != 0) {
DEBUG ((EFI_D_ERROR, " Instruction %a at 0x%08x\n", FaultStatusToString (SystemContext.SystemContextArm->IFSR & 0xf), SystemContext.SystemContextArm->IFAR));
} }
DEBUG ((EFI_D_ERROR, "\n")); DEBUG ((EFI_D_ERROR, "\n"));

2
ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c
View File

@ -609,7 +609,7 @@ UncachedSafeFreePool (
**/ **/
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI
DebugUncachedMemoryAllocationLibConstructor ( UncachedMemoryAllocationLibConstructor (
IN EFI_HANDLE ImageHandle, IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable IN EFI_SYSTEM_TABLE *SystemTable
) )

4
ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
View File

@ -20,6 +20,7 @@
MODULE_TYPE = DXE_DRIVER MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0 VERSION_STRING = 1.0
LIBRARY_CLASS = UncachedMemoryAllocationLib LIBRARY_CLASS = UncachedMemoryAllocationLib
CONSTRUCTOR = UncachedMemoryAllocationLibConstructor
[Sources.common] [Sources.common]
UncachedMemoryAllocationLib.c UncachedMemoryAllocationLib.c
@ -37,4 +38,5 @@
MemoryAllocationLib MemoryAllocationLib
DxeServicesTableLib DxeServicesTableLib
[Depex]
gEfiCpuArchProtocolGuid