UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enable

Current X2APIC is enabled in MpInitLib (used by CpuMpPei and CpuDxe) to follow
SDM suggestion. That means we only enable X2APIC if we found there are any
initial CPU ID value >= 255.

This patch is to provide one chance for platform to enable X2APIC even there is
no any initial CPU ID value >= 255.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Jeff Fan 2017-05-24 13:45:25 +08:00
parent df642d70e3
commit 6661abb695
3 changed files with 77 additions and 10 deletions

View File

@ -797,6 +797,21 @@ C1eInitialize (
IN BOOLEAN State
);
/**
Prepares for the data used by CPU feature detection and initialization.
@param[in] NumberOfProcessors The number of CPUs in the platform.
@return Pointer to a buffer of CPU related configuration data.
@note This service could be called by BSP only.
**/
VOID *
EFIAPI
X2ApicGetConfigData (
IN UINTN NumberOfProcessors
);
/**
Detects if X2Apci feature supported on current processor.

View File

@ -211,7 +211,7 @@ CpuCommonFeaturesLibConstructor (
if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {
Status = RegisterCpuFeature (
"X2Apic",
NULL,
X2ApicGetConfigData,
X2ApicSupport,
X2ApicInitialize,
CPU_FEATURE_X2APIC,

View File

@ -14,6 +14,28 @@
#include "CpuCommonFeatures.h"
/**
Prepares for the data used by CPU feature detection and initialization.
@param[in] NumberOfProcessors The number of CPUs in the platform.
@return Pointer to a buffer of CPU related configuration data.
@note This service could be called by BSP only.
**/
VOID *
EFIAPI
X2ApicGetConfigData (
IN UINTN NumberOfProcessors
)
{
BOOLEAN *ConfigData;
ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);
ASSERT (ConfigData != NULL);
return ConfigData;
}
/**
Detects if X2Apci feature supported on current processor.
@ -40,7 +62,16 @@ X2ApicSupport (
IN VOID *ConfigData OPTIONAL
)
{
return (GetApicMode () == LOCAL_APIC_MODE_X2APIC);
BOOLEAN *X2ApicEnabled;
ASSERT (ConfigData != NULL);
X2ApicEnabled = (BOOLEAN *) ConfigData;
//
// *ConfigData indicates if X2APIC enabled on current processor
//
X2ApicEnabled[ProcessorNumber] = (GetApicMode () == LOCAL_APIC_MODE_X2APIC) ? TRUE : FALSE;
return (CpuInfo->CpuIdVersionInfoEcx.Bits.x2APIC == 1);
}
/**
@ -69,13 +100,34 @@ X2ApicInitialize (
IN BOOLEAN State
)
{
PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_APIC_BASE,
MSR_IA32_APIC_BASE_REGISTER,
Bits.EXTD,
(State) ? 1 : 0
);
BOOLEAN *X2ApicEnabled;
ASSERT (ConfigData != NULL);
X2ApicEnabled = (BOOLEAN *) ConfigData;
if (X2ApicEnabled[ProcessorNumber]) {
PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_APIC_BASE,
MSR_IA32_APIC_BASE_REGISTER,
Bits.EXTD,
1
);
} else {
//
// Enable X2APIC mode only if X2APIC is not enabled,
// Needn't to disabe X2APIC mode again if X2APIC is not enabled
//
if (State) {
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_APIC_BASE,
MSR_IA32_APIC_BASE_REGISTER,
Bits.EXTD,
1
);
}
}
return RETURN_SUCCESS;
}