mirror of https://github.com/acidanthera/audk.git
OvmfPkg/SmmAccess: support extended TSEG size
In SmmAccessPeiEntryPoint(), map TSEG megabyte counts different from 1, 2 and 8 to the MCH_ESMRAMC_TSEG_EXT bit pattern (introduced in the previous patch), for the ESMRAMC.TSEG_SZ bit-field register. (Suggested by Jordan.) In SmramAccessGetCapabilities() -- backing both PEI_SMM_ACCESS_PPI.GetCapabilities() and EFI_SMM_ACCESS2_PROTOCOL.GetCapabilities() --, map the MCH_ESMRAMC_TSEG_EXT bit pattern found in the ESMRAMC.TSEG_SZ bit-field register to a byte count of (mQ35TsegMbytes * SIZE_1MB). (MCH_ESMRAMC_TSEG_EXT is the only possible pattern if none of MCH_ESMRAMC_TSEG_1MB, MCH_ESMRAMC_TSEG_2MB, and MCH_ESMRAMC_TSEG_8MB match.) The new code paths are not exercised just yet; for that, PlatformPei is going to have to set PcdQ35TsegMbytes (and consequently, SmramInternal's "mQ35TsegMbytes") to a value different from 1, 2, and 8. Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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@ -330,7 +330,8 @@ SmmAccessPeiEntryPoint (
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EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;
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EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB :
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mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB :
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MCH_ESMRAMC_TSEG_1MB;
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mQ35TsegMbytes == 1 ? MCH_ESMRAMC_TSEG_1MB :
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MCH_ESMRAMC_TSEG_EXT;
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EsmramcVal |= MCH_ESMRAMC_T_EN;
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PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);
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@ -198,7 +198,9 @@ SmramAccessGetCapabilities (
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SmramMap[DescIdxMain].PhysicalSize =
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(TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :
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TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :
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SIZE_1MB) - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
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TsegSizeBits == MCH_ESMRAMC_TSEG_1MB ? SIZE_1MB :
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mQ35TsegMbytes * SIZE_1MB) -
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SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
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SmramMap[DescIdxMain].RegionState = CommonRegionState;
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return EFI_SUCCESS;
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