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MdePkg: Added support for SMBIOS spec v3.6.0 to Smbios.h 

Updated SmBios.h with new fields added as part of SMBIOS 3.6.0 spec update.

Signed-off-by: Sainadh Nagolu <sainadhn@ami.com>
Cc: Vasudevan Sambandan <vasudevans@ami.com>
Cc: Sundaresan S <sundaresans@ami.com>
Reviewed-by: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Sainadh Nagolu 2022-08-17 13:08:28 +05:30 committed by mergify[bot]
parent 35d167ef3c
commit 68bf712d4f
1 changed files with 66 additions and 32 deletions
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98
MdePkg/Include/IndustryStandard/SmBios.h
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@ -1,5 +1,5 @@
/** @file
Industry Standard Definitions of SMBIOS Table Specification v3.5.0.
Industry Standard Definitions of SMBIOS Table Specification v3.6.0.
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
(C) Copyright 2015-2017 Hewlett Packard Enterprise Development LP<BR>
@ -723,21 +723,39 @@ typedef enum {
/// Processor Information2 - Processor Family2.
///
typedef enum {
ProcessorFamilyARMv7 = 0x0100,
ProcessorFamilyARMv8 = 0x0101,
ProcessorFamilySH3 = 0x0104,
ProcessorFamilySH4 = 0x0105,
ProcessorFamilyARM = 0x0118,
ProcessorFamilyStrongARM = 0x0119,
ProcessorFamily6x86 = 0x012C,
ProcessorFamilyMediaGX = 0x012D,
ProcessorFamilyMII = 0x012E,
ProcessorFamilyWinChip = 0x0140,
ProcessorFamilyDSP = 0x015E,
ProcessorFamilyVideoProcessor = 0x01F4,
ProcessorFamilyRiscvRV32 = 0x0200,
ProcessorFamilyRiscVRV64 = 0x0201,
ProcessorFamilyRiscVRV128 = 0x0202
ProcessorFamilyARMv7 = 0x0100,
ProcessorFamilyARMv8 = 0x0101,
ProcessorFamilyARMv9 = 0x0102,
ProcessorFamilySH3 = 0x0104,
ProcessorFamilySH4 = 0x0105,
ProcessorFamilyARM = 0x0118,
ProcessorFamilyStrongARM = 0x0119,
ProcessorFamily6x86 = 0x012C,
ProcessorFamilyMediaGX = 0x012D,
ProcessorFamilyMII = 0x012E,
ProcessorFamilyWinChip = 0x0140,
ProcessorFamilyDSP = 0x015E,
ProcessorFamilyVideoProcessor = 0x01F4,
ProcessorFamilyRiscvRV32 = 0x0200,
ProcessorFamilyRiscVRV64 = 0x0201,
ProcessorFamilyRiscVRV128 = 0x0202,
ProcessorFamilyLoongArch = 0x0258,
ProcessorFamilyLoongson1 = 0x0259,
ProcessorFamilyLoongson2 = 0x025A,
ProcessorFamilyLoongson3 = 0x025B,
ProcessorFamilyLoongson2K = 0x025C,
ProcessorFamilyLoongson3A = 0x025D,
ProcessorFamilyLoongson3B = 0x025E,
ProcessorFamilyLoongson3C = 0x025F,
ProcessorFamilyLoongson3D = 0x0260,
ProcessorFamilyLoongson3E = 0x0261,
ProcessorFamilyDualCoreLoongson2K = 0x0262,
ProcessorFamilyQuadCoreLoongson3A = 0x026C,
ProcessorFamilyMultiCoreLoongson3A = 0x026D,
ProcessorFamilyQuadCoreLoongson3B = 0x026E,
ProcessorFamilyMultiCoreLoongson3B = 0x026F,
ProcessorFamilyMultiCoreLoongson3C = 0x0270,
ProcessorFamilyMultiCoreLoongson3D = 0x0271
} PROCESSOR_FAMILY2_DATA;
///
@ -818,7 +836,16 @@ typedef enum {
ProcessorUpgradeSocketBGA1528 = 0x3C,
ProcessorUpgradeSocketLGA4189 = 0x3D,
ProcessorUpgradeSocketLGA1200 = 0x3E,
ProcessorUpgradeSocketLGA4677 = 0x3F
ProcessorUpgradeSocketLGA4677 = 0x3F,
ProcessorUpgradeSocketLGA1700 = 0x40,
ProcessorUpgradeSocketBGA1744 = 0x41,
ProcessorUpgradeSocketBGA1781 = 0x42,
ProcessorUpgradeSocketBGA1211 = 0x43,
ProcessorUpgradeSocketBGA2422 = 0x44,
ProcessorUpgradeSocketLGA1211 = 0x45,
ProcessorUpgradeSocketLGA2422 = 0x46,
ProcessorUpgradeSocketLGA5773 = 0x47,
ProcessorUpgradeSocketBGA5773 = 0x48
} PROCESSOR_UPGRADE;
///
@ -826,12 +853,12 @@ typedef enum {
///
typedef struct {
UINT32 ProcessorSteppingId : 4;
UINT32 ProcessorModel : 4;
UINT32 ProcessorFamily : 4;
UINT32 ProcessorType : 2;
UINT32 ProcessorModel : 4;
UINT32 ProcessorFamily : 4;
UINT32 ProcessorType : 2;
UINT32 ProcessorReserved1 : 2;
UINT32 ProcessorXModel : 4;
UINT32 ProcessorXFamily : 8;
UINT32 ProcessorXModel : 4;
UINT32 ProcessorXFamily : 8;
UINT32 ProcessorReserved2 : 4;
} PROCESSOR_SIGNATURE;
@ -947,6 +974,10 @@ typedef struct {
UINT16 CoreCount2;
UINT16 EnabledCoreCount2;
UINT16 ThreadCount2;
//
// Add for smbios 3.6
//
UINT16 ThreadEnabled;
} SMBIOS_TABLE_TYPE4;
///
@ -1823,7 +1854,8 @@ typedef enum {
MemoryTypeHBM = 0x20,
MemoryTypeHBM2 = 0x21,
MemoryTypeDdr5 = 0x22,
MemoryTypeLpddr5 = 0x23
MemoryTypeLpddr5 = 0x23,
MemoryTypeHBM3 = 0x24
} MEMORY_DEVICE_TYPE;
///
@ -2672,15 +2704,17 @@ typedef struct {
/// Processor Specific Block - Processor Architecture Type
///
typedef enum {
ProcessorSpecificBlockArchTypeReserved = 0x00,
ProcessorSpecificBlockArchTypeIa32 = 0x01,
ProcessorSpecificBlockArchTypeX64 = 0x02,
ProcessorSpecificBlockArchTypeItanium = 0x03,
ProcessorSpecificBlockArchTypeAarch32 = 0x04,
ProcessorSpecificBlockArchTypeAarch64 = 0x05,
ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06,
ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07,
ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08
ProcessorSpecificBlockArchTypeReserved = 0x00,
ProcessorSpecificBlockArchTypeIa32 = 0x01,
ProcessorSpecificBlockArchTypeX64 = 0x02,
ProcessorSpecificBlockArchTypeItanium = 0x03,
ProcessorSpecificBlockArchTypeAarch32 = 0x04,
ProcessorSpecificBlockArchTypeAarch64 = 0x05,
ProcessorSpecificBlockArchTypeRiscVRV32 = 0x06,
ProcessorSpecificBlockArchTypeRiscVRV64 = 0x07,
ProcessorSpecificBlockArchTypeRiscVRV128 = 0x08,
ProcessorSpecificBlockArchTypeLoongArch32 = 0x09,
ProcessorSpecificBlockArchTypeLoongArch64 = 0x0A
} PROCESSOR_SPECIFIC_BLOCK_ARCH_TYPE;
///