mirror of https://github.com/acidanthera/audk.git
CorebootPayloadPkg: Use generic PciBus/PciHostBridge driver
Current CorebootPayloadPkg uses PciBusNoEnumerationDxe and PciRootBridgenoEnumerationDxe copied from the DuetPkg. Now it will switch to use the standard PciBusDxe and PciHostBridgeDxe from MdeModulePkg. As a result, a coreboot specific PciHostBridgeLib is added to collect pre-allocated PCI resources. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
This commit is contained in:
Maurice Ma
parent
60c809f362
commit
69787a9d31
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@ -111,8 +111,8 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
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#
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#
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# PCI Support
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# PCI Support
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#
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#
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INF CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
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INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
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INF CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
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INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
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#
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#
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# ISA Support
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# ISA Support
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@ -38,6 +38,11 @@
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#
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#
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DEFINE MAX_LOGICAL_PROCESSORS = 64
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DEFINE MAX_LOGICAL_PROCESSORS = 64
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#
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# PCI options
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#
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DEFINE PCIE_BASE = 0xE0000000
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#
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#
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# Serial port set up
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# Serial port set up
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#
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#
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@ -115,8 +120,9 @@
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PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
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PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
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CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
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CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
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IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
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IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
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PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
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PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
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PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
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PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
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PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
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PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
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PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
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PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
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PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
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CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
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CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
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@ -251,6 +257,8 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
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gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
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gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)
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!if $(SOURCE_DEBUG_ENABLE)
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!if $(SOURCE_DEBUG_ENABLE)
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gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
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gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
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!endif
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!endif
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@ -282,6 +290,7 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
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gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)
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@ -418,8 +427,11 @@
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#
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#
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# PCI Support
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# PCI Support
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#
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#
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CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
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MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
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CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
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MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
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<LibraryClasses>
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PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
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}
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#
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#
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# SCSI/ATA/IDE/DISK Support
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# SCSI/ATA/IDE/DISK Support
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@ -38,6 +38,11 @@
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#
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#
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DEFINE MAX_LOGICAL_PROCESSORS = 64
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DEFINE MAX_LOGICAL_PROCESSORS = 64
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#
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# PCI options
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#
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DEFINE PCIE_BASE = 0xE0000000
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#
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#
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# Serial port set up
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# Serial port set up
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#
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#
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@ -117,8 +122,9 @@
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PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
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PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
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CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
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CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
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IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
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IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
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PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
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PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
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PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
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PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
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PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
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PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
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PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
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PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
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PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
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CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
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CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
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@ -254,6 +260,8 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
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gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
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gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
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gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE)
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!if $(SOURCE_DEBUG_ENABLE)
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!if $(SOURCE_DEBUG_ENABLE)
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gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
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gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
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!endif
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!endif
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@ -285,6 +293,7 @@
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL)
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
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gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE)
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gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)
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gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)
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@ -421,8 +430,11 @@
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#
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#
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# PCI Support
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# PCI Support
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#
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#
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CorebootModulePkg/PciRootBridgeNoEnumerationDxe/PciRootBridgeNoEnumeration.inf
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MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
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CorebootModulePkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
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MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
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<LibraryClasses>
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PciHostBridgeLib|CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
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}
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#
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#
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# SCSI/ATA/IDE/DISK Support
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# SCSI/ATA/IDE/DISK Support
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@ -0,0 +1,86 @@
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/** @file
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Header file of PciHostBridgeLib.
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Copyright (C) 2016, Red Hat, Inc.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
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WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _PCI_HOST_BRIDGE_H
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#define _PCI_HOST_BRIDGE_H
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typedef struct {
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ACPI_HID_DEVICE_PATH AcpiDevicePath;
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EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
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} CB_PCI_ROOT_BRIDGE_DEVICE_PATH;
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PCI_ROOT_BRIDGE *
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ScanForRootBridges (
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UINTN *NumberOfRootBridges
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);
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/**
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Initialize a PCI_ROOT_BRIDGE structure.
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@param[in] Supports Supported attributes.
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@param[in] Attributes Initial attributes.
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@param[in] AllocAttributes Allocation attributes.
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@param[in] RootBusNumber The bus number to store in RootBus.
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@param[in] MaxSubBusNumber The inclusive maximum bus number that can be
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assigned to any subordinate bus found behind any
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PCI bridge hanging off this root bus.
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The caller is repsonsible for ensuring that
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RootBusNumber <= MaxSubBusNumber. If
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RootBusNumber equals MaxSubBusNumber, then the
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root bus has no room for subordinate buses.
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@param[in] Io IO aperture.
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@param[in] Mem MMIO aperture.
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@param[in] MemAbove4G MMIO aperture above 4G.
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@param[in] PMem Prefetchable MMIO aperture.
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@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
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@param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the
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caller) that should be filled in by this
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function.
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@retval EFI_SUCCESS Initialization successful. A device path
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consisting of an ACPI device path node, with
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UID = RootBusNumber, has been allocated and
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linked into RootBus.
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@retval EFI_OUT_OF_RESOURCES Memory allocation failed.
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**/
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EFI_STATUS
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InitRootBridge (
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IN UINT64 Supports,
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IN UINT64 Attributes,
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IN UINT64 AllocAttributes,
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IN UINT8 RootBusNumber,
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IN UINT8 MaxSubBusNumber,
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IN PCI_ROOT_BRIDGE_APERTURE *Io,
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IN PCI_ROOT_BRIDGE_APERTURE *Mem,
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IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
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IN PCI_ROOT_BRIDGE_APERTURE *PMem,
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IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
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OUT PCI_ROOT_BRIDGE *RootBus
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);
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#endif
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@ -0,0 +1,228 @@
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/** @file
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Library instance of PciHostBridgeLib library class for coreboot.
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Copyright (C) 2016, Red Hat, Inc.
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Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php.
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
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WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#include <PiDxe.h>
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#include <IndustryStandard/Pci.h>
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#include <Protocol/PciHostBridgeResourceAllocation.h>
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#include <Protocol/PciRootBridgeIo.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/DebugLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/PciHostBridgeLib.h>
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#include <Library/PciLib.h>
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#include "PciHostBridge.h"
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STATIC
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CONST
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CB_PCI_ROOT_BRIDGE_DEVICE_PATH mRootBridgeDevicePathTemplate = {
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{
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{
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ACPI_DEVICE_PATH,
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ACPI_DP,
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{
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(UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
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(UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
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}
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},
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EISA_PNP_ID(0x0A03), // HID
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0 // UID
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},
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{
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END_DEVICE_PATH_TYPE,
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END_ENTIRE_DEVICE_PATH_SUBTYPE,
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{
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END_DEVICE_PATH_LENGTH,
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0
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}
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}
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};
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/**
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Initialize a PCI_ROOT_BRIDGE structure.
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@param[in] Supports Supported attributes.
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@param[in] Attributes Initial attributes.
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@param[in] AllocAttributes Allocation attributes.
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@param[in] RootBusNumber The bus number to store in RootBus.
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@param[in] MaxSubBusNumber The inclusive maximum bus number that can be
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assigned to any subordinate bus found behind any
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PCI bridge hanging off this root bus.
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The caller is repsonsible for ensuring that
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RootBusNumber <= MaxSubBusNumber. If
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RootBusNumber equals MaxSubBusNumber, then the
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root bus has no room for subordinate buses.
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@param[in] Io IO aperture.
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@param[in] Mem MMIO aperture.
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@param[in] MemAbove4G MMIO aperture above 4G.
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@param[in] PMem Prefetchable MMIO aperture.
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@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
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@param[out] RootBus The PCI_ROOT_BRIDGE structure (allocated by the
|
||||||
|
caller) that should be filled in by this
|
||||||
|
function.
|
||||||
|
|
||||||
|
@retval EFI_SUCCESS Initialization successful. A device path
|
||||||
|
consisting of an ACPI device path node, with
|
||||||
|
UID = RootBusNumber, has been allocated and
|
||||||
|
linked into RootBus.
|
||||||
|
|
||||||
|
@retval EFI_OUT_OF_RESOURCES Memory allocation failed.
|
||||||
|
**/
|
||||||
|
EFI_STATUS
|
||||||
|
InitRootBridge (
|
||||||
|
IN UINT64 Supports,
|
||||||
|
IN UINT64 Attributes,
|
||||||
|
IN UINT64 AllocAttributes,
|
||||||
|
IN UINT8 RootBusNumber,
|
||||||
|
IN UINT8 MaxSubBusNumber,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *Io,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G,
|
||||||
|
OUT PCI_ROOT_BRIDGE *RootBus
|
||||||
|
)
|
||||||
|
{
|
||||||
|
CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Be safe if other fields are added to PCI_ROOT_BRIDGE later.
|
||||||
|
//
|
||||||
|
ZeroMem (RootBus, sizeof *RootBus);
|
||||||
|
|
||||||
|
RootBus->Segment = 0;
|
||||||
|
|
||||||
|
RootBus->Supports = Supports;
|
||||||
|
RootBus->Attributes = Attributes;
|
||||||
|
|
||||||
|
RootBus->DmaAbove4G = FALSE;
|
||||||
|
|
||||||
|
RootBus->AllocationAttributes = AllocAttributes;
|
||||||
|
RootBus->Bus.Base = RootBusNumber;
|
||||||
|
RootBus->Bus.Limit = MaxSubBusNumber;
|
||||||
|
CopyMem (&RootBus->Io, Io, sizeof (*Io));
|
||||||
|
CopyMem (&RootBus->Mem, Mem, sizeof (*Mem));
|
||||||
|
CopyMem (&RootBus->MemAbove4G, MemAbove4G, sizeof (*MemAbove4G));
|
||||||
|
CopyMem (&RootBus->PMem, PMem, sizeof (*PMem));
|
||||||
|
CopyMem (&RootBus->PMemAbove4G, PMemAbove4G, sizeof (*PMemAbove4G));
|
||||||
|
|
||||||
|
RootBus->NoExtendedConfigSpace = FALSE;
|
||||||
|
|
||||||
|
DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),
|
||||||
|
&mRootBridgeDevicePathTemplate);
|
||||||
|
if (DevicePath == NULL) {
|
||||||
|
DEBUG ((EFI_D_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES));
|
||||||
|
return EFI_OUT_OF_RESOURCES;
|
||||||
|
}
|
||||||
|
DevicePath->AcpiDevicePath.UID = RootBusNumber;
|
||||||
|
RootBus->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;
|
||||||
|
|
||||||
|
DEBUG ((EFI_D_INFO,
|
||||||
|
"%a: populated root bus %d, with room for %d subordinate bus(es)\n",
|
||||||
|
__FUNCTION__, RootBusNumber, MaxSubBusNumber - RootBusNumber));
|
||||||
|
return EFI_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
Return all the root bridge instances in an array.
|
||||||
|
|
||||||
|
@param Count Return the count of root bridge instances.
|
||||||
|
|
||||||
|
@return All the root bridge instances in an array.
|
||||||
|
The array should be passed into PciHostBridgeFreeRootBridges()
|
||||||
|
when it's not used.
|
||||||
|
**/
|
||||||
|
PCI_ROOT_BRIDGE *
|
||||||
|
EFIAPI
|
||||||
|
PciHostBridgeGetRootBridges (
|
||||||
|
UINTN *Count
|
||||||
|
)
|
||||||
|
{
|
||||||
|
return ScanForRootBridges (Count);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
Free the root bridge instances array returned from
|
||||||
|
PciHostBridgeGetRootBridges().
|
||||||
|
|
||||||
|
@param The root bridge instances array.
|
||||||
|
@param The count of the array.
|
||||||
|
**/
|
||||||
|
VOID
|
||||||
|
EFIAPI
|
||||||
|
PciHostBridgeFreeRootBridges (
|
||||||
|
PCI_ROOT_BRIDGE *Bridges,
|
||||||
|
UINTN Count
|
||||||
|
)
|
||||||
|
{
|
||||||
|
if (Bridges == NULL && Count == 0) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
ASSERT (Bridges != NULL && Count > 0);
|
||||||
|
|
||||||
|
do {
|
||||||
|
--Count;
|
||||||
|
FreePool (Bridges[Count].DevicePath);
|
||||||
|
} while (Count > 0);
|
||||||
|
|
||||||
|
FreePool (Bridges);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
Inform the platform that the resource conflict happens.
|
||||||
|
|
||||||
|
@param HostBridgeHandle Handle of the Host Bridge.
|
||||||
|
@param Configuration Pointer to PCI I/O and PCI memory resource
|
||||||
|
descriptors. The Configuration contains the resources
|
||||||
|
for all the root bridges. The resource for each root
|
||||||
|
bridge is terminated with END descriptor and an
|
||||||
|
additional END is appended indicating the end of the
|
||||||
|
entire resources. The resource descriptor field
|
||||||
|
values follow the description in
|
||||||
|
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
|
||||||
|
.SubmitResources().
|
||||||
|
**/
|
||||||
|
VOID
|
||||||
|
EFIAPI
|
||||||
|
PciHostBridgeResourceConflict (
|
||||||
|
EFI_HANDLE HostBridgeHandle,
|
||||||
|
VOID *Configuration
|
||||||
|
)
|
||||||
|
{
|
||||||
|
//
|
||||||
|
// coreboot UEFI Payload does not do PCI enumeration and should not call this
|
||||||
|
// library interface.
|
||||||
|
//
|
||||||
|
ASSERT (FALSE);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,47 @@
|
||||||
|
## @file
|
||||||
|
# Library instance of PciHostBridgeLib library class for coreboot.
|
||||||
|
#
|
||||||
|
# Copyright (C) 2016, Red Hat, Inc.
|
||||||
|
# Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||||
|
#
|
||||||
|
# This program and the accompanying materials are licensed and made available
|
||||||
|
# under the terms and conditions of the BSD License which accompanies this
|
||||||
|
# distribution. The full text of the license may be found at
|
||||||
|
# http://opensource.org/licenses/bsd-license.php
|
||||||
|
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||||
|
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
|
||||||
|
# IMPLIED.
|
||||||
|
#
|
||||||
|
#
|
||||||
|
##
|
||||||
|
|
||||||
|
[Defines]
|
||||||
|
INF_VERSION = 0x00010005
|
||||||
|
BASE_NAME = PciHostBridgeLib
|
||||||
|
FILE_GUID = 62EE5269-CFFD-43a3-BE3F-622FC79F467E
|
||||||
|
MODULE_TYPE = BASE
|
||||||
|
VERSION_STRING = 1.0
|
||||||
|
LIBRARY_CLASS = PciHostBridgeLib
|
||||||
|
|
||||||
|
#
|
||||||
|
# The following information is for reference only and not required by the build
|
||||||
|
# tools.
|
||||||
|
#
|
||||||
|
# VALID_ARCHITECTURES = IA32 X64 IPF EBC
|
||||||
|
#
|
||||||
|
|
||||||
|
[Sources]
|
||||||
|
PciHostBridge.h
|
||||||
|
PciHostBridgeLib.c
|
||||||
|
PciHostBridgeSupport.c
|
||||||
|
|
||||||
|
[Packages]
|
||||||
|
MdeModulePkg/MdeModulePkg.dec
|
||||||
|
MdePkg/MdePkg.dec
|
||||||
|
|
||||||
|
[LibraryClasses]
|
||||||
|
BaseMemoryLib
|
||||||
|
DebugLib
|
||||||
|
DevicePathLib
|
||||||
|
MemoryAllocationLib
|
||||||
|
PciLib
|
||||||
|
|
@ -0,0 +1,581 @@
|
||||||
|
/** @file
|
||||||
|
Scan the entire PCI bus for root bridges to support coreboot UEFI payload.
|
||||||
|
|
||||||
|
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
|
||||||
|
|
||||||
|
This program and the accompanying materials are licensed and made available
|
||||||
|
under the terms and conditions of the BSD License which accompanies this
|
||||||
|
distribution. The full text of the license may be found at
|
||||||
|
http://opensource.org/licenses/bsd-license.php.
|
||||||
|
|
||||||
|
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
|
||||||
|
WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||||
|
|
||||||
|
**/
|
||||||
|
|
||||||
|
#include <PiDxe.h>
|
||||||
|
#include <IndustryStandard/Pci.h>
|
||||||
|
#include <Protocol/PciHostBridgeResourceAllocation.h>
|
||||||
|
#include <Protocol/PciRootBridgeIo.h>
|
||||||
|
#include <Library/BaseMemoryLib.h>
|
||||||
|
#include <Library/DebugLib.h>
|
||||||
|
#include <Library/MemoryAllocationLib.h>
|
||||||
|
#include <Library/PciHostBridgeLib.h>
|
||||||
|
#include <Library/PciLib.h>
|
||||||
|
#include "PciHostBridge.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
Adjust the collected PCI resource.
|
||||||
|
|
||||||
|
@param[in] Io IO aperture.
|
||||||
|
|
||||||
|
@param[in] Mem MMIO aperture.
|
||||||
|
|
||||||
|
@param[in] MemAbove4G MMIO aperture above 4G.
|
||||||
|
|
||||||
|
@param[in] PMem Prefetchable MMIO aperture.
|
||||||
|
|
||||||
|
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
|
||||||
|
**/
|
||||||
|
VOID
|
||||||
|
AdjustRootBridgeResource (
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *Io,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
|
||||||
|
)
|
||||||
|
{
|
||||||
|
UINT64 Mask;
|
||||||
|
|
||||||
|
//
|
||||||
|
// For now try to downgrade everything into MEM32 since
|
||||||
|
// - coreboot does not assign resource above 4GB
|
||||||
|
// - coreboot might allocate interleaved MEM32 and PMEM32 resource
|
||||||
|
// in some cases
|
||||||
|
//
|
||||||
|
if (PMem->Base < Mem->Base) {
|
||||||
|
Mem->Base = PMem->Base;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (PMem->Limit > Mem->Limit) {
|
||||||
|
Mem->Limit = PMem->Limit;
|
||||||
|
}
|
||||||
|
|
||||||
|
PMem->Base = MAX_UINT64;
|
||||||
|
PMem->Limit = 0;
|
||||||
|
|
||||||
|
if (MemAbove4G->Base < 0x100000000ULL) {
|
||||||
|
if (MemAbove4G->Base < Mem->Base) {
|
||||||
|
Mem->Base = MemAbove4G->Base;
|
||||||
|
}
|
||||||
|
if (MemAbove4G->Limit > Mem->Limit) {
|
||||||
|
Mem->Limit = MemAbove4G->Limit;
|
||||||
|
}
|
||||||
|
MemAbove4G->Base = MAX_UINT64;
|
||||||
|
MemAbove4G->Limit = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (PMemAbove4G->Base < 0x100000000ULL) {
|
||||||
|
if (PMemAbove4G->Base < Mem->Base) {
|
||||||
|
Mem->Base = PMemAbove4G->Base;
|
||||||
|
}
|
||||||
|
if (PMemAbove4G->Limit > Mem->Limit) {
|
||||||
|
Mem->Limit = PMemAbove4G->Limit;
|
||||||
|
}
|
||||||
|
PMemAbove4G->Base = MAX_UINT64;
|
||||||
|
PMemAbove4G->Limit = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Align IO resource at 4K boundary
|
||||||
|
//
|
||||||
|
Mask = 0xFFFULL;
|
||||||
|
Io->Limit = (Io->Limit + Mask) & ~Mask;
|
||||||
|
if (Io->Base != MAX_UINT64) {
|
||||||
|
Io->Base &= ~Mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Align MEM resource at 1MB boundary
|
||||||
|
//
|
||||||
|
Mask = 0xFFFFFULL;
|
||||||
|
Mem->Limit = (Mem->Limit + Mask) & ~Mask;
|
||||||
|
if (Mem->Base != MAX_UINT64) {
|
||||||
|
Mem->Base &= ~Mask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
Probe a bar is existed or not.
|
||||||
|
|
||||||
|
@param[in] Address PCI address for the BAR.
|
||||||
|
@param[out] OriginalValue The original bar value returned.
|
||||||
|
@param[out] Value The probed bar value returned.
|
||||||
|
**/
|
||||||
|
STATIC
|
||||||
|
VOID
|
||||||
|
PcatPciRootBridgeBarExisted (
|
||||||
|
IN UINT64 Address,
|
||||||
|
OUT UINT32 *OriginalValue,
|
||||||
|
OUT UINT32 *Value
|
||||||
|
)
|
||||||
|
{
|
||||||
|
UINTN PciAddress;
|
||||||
|
|
||||||
|
PciAddress = (UINTN)Address;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Preserve the original value
|
||||||
|
//
|
||||||
|
*OriginalValue = PciRead32 (PciAddress);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Disable timer interrupt while the BAR is probed
|
||||||
|
//
|
||||||
|
DisableInterrupts ();
|
||||||
|
|
||||||
|
PciWrite32 (PciAddress, 0xFFFFFFFF);
|
||||||
|
*Value = PciRead32 (PciAddress);
|
||||||
|
PciWrite32 (PciAddress, *OriginalValue);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Enable interrupt
|
||||||
|
//
|
||||||
|
EnableInterrupts ();
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
Parse PCI bar and collect the assigned PCI resouce information.
|
||||||
|
|
||||||
|
@param[in] Command Supported attributes.
|
||||||
|
|
||||||
|
@param[in] Bus PCI bus number.
|
||||||
|
|
||||||
|
@param[in] Device PCI device number.
|
||||||
|
|
||||||
|
@param[in] Function PCI function number.
|
||||||
|
|
||||||
|
@param[in] BarOffsetBase PCI bar start offset.
|
||||||
|
|
||||||
|
@param[in] BarOffsetEnd PCI bar end offset.
|
||||||
|
|
||||||
|
@param[in] Io IO aperture.
|
||||||
|
|
||||||
|
@param[in] Mem MMIO aperture.
|
||||||
|
|
||||||
|
@param[in] MemAbove4G MMIO aperture above 4G.
|
||||||
|
|
||||||
|
@param[in] PMem Prefetchable MMIO aperture.
|
||||||
|
|
||||||
|
@param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.
|
||||||
|
**/
|
||||||
|
STATIC
|
||||||
|
VOID
|
||||||
|
PcatPciRootBridgeParseBars (
|
||||||
|
IN UINT16 Command,
|
||||||
|
IN UINTN Bus,
|
||||||
|
IN UINTN Device,
|
||||||
|
IN UINTN Function,
|
||||||
|
IN UINTN BarOffsetBase,
|
||||||
|
IN UINTN BarOffsetEnd,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *Io,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *Mem,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *PMem,
|
||||||
|
IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G
|
||||||
|
|
||||||
|
)
|
||||||
|
{
|
||||||
|
UINT32 OriginalValue;
|
||||||
|
UINT32 Value;
|
||||||
|
UINT32 OriginalUpperValue;
|
||||||
|
UINT32 UpperValue;
|
||||||
|
UINT64 Mask;
|
||||||
|
UINTN Offset;
|
||||||
|
UINT64 Base;
|
||||||
|
UINT64 Length;
|
||||||
|
UINT64 Limit;
|
||||||
|
PCI_ROOT_BRIDGE_APERTURE *MemAperture;
|
||||||
|
|
||||||
|
for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {
|
||||||
|
PcatPciRootBridgeBarExisted (
|
||||||
|
PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
|
||||||
|
&OriginalValue, &Value
|
||||||
|
);
|
||||||
|
if (Value == 0) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if ((Value & BIT0) == BIT0) {
|
||||||
|
//
|
||||||
|
// IO Bar
|
||||||
|
//
|
||||||
|
if (Command & EFI_PCI_COMMAND_IO_SPACE) {
|
||||||
|
Mask = 0xfffffffc;
|
||||||
|
Base = OriginalValue & Mask;
|
||||||
|
Length = ((~(Value & Mask)) & Mask) + 0x04;
|
||||||
|
if (!(Value & 0xFFFF0000)) {
|
||||||
|
Length &= 0x0000FFFF;
|
||||||
|
}
|
||||||
|
Limit = Base + Length - 1;
|
||||||
|
|
||||||
|
if ((Base > 0) && (Base < Limit)) {
|
||||||
|
if (Io->Base > Base) {
|
||||||
|
Io->Base = Base;
|
||||||
|
}
|
||||||
|
if (Io->Limit < Limit) {
|
||||||
|
Io->Limit = Limit;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
//
|
||||||
|
// Mem Bar
|
||||||
|
//
|
||||||
|
if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {
|
||||||
|
|
||||||
|
Mask = 0xfffffff0;
|
||||||
|
Base = OriginalValue & Mask;
|
||||||
|
Length = Value & Mask;
|
||||||
|
|
||||||
|
if ((Value & (BIT1 | BIT2)) == 0) {
|
||||||
|
//
|
||||||
|
// 32bit
|
||||||
|
//
|
||||||
|
Length = ((~Length) + 1) & 0xffffffff;
|
||||||
|
|
||||||
|
if ((Value & BIT3) == BIT3) {
|
||||||
|
MemAperture = PMem;
|
||||||
|
} else {
|
||||||
|
MemAperture = Mem;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
//
|
||||||
|
// 64bit
|
||||||
|
//
|
||||||
|
Offset += 4;
|
||||||
|
PcatPciRootBridgeBarExisted (
|
||||||
|
PCI_LIB_ADDRESS (Bus, Device, Function, Offset),
|
||||||
|
&OriginalUpperValue,
|
||||||
|
&UpperValue
|
||||||
|
);
|
||||||
|
|
||||||
|
Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);
|
||||||
|
Length = Length | LShiftU64 ((UINT64) UpperValue, 32);
|
||||||
|
Length = (~Length) + 1;
|
||||||
|
|
||||||
|
if ((Value & BIT3) == BIT3) {
|
||||||
|
MemAperture = PMemAbove4G;
|
||||||
|
} else {
|
||||||
|
MemAperture = MemAbove4G;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
Limit = Base + Length - 1;
|
||||||
|
if ((Base > 0) && (Base < Limit)) {
|
||||||
|
if (MemAperture->Base > Base) {
|
||||||
|
MemAperture->Base = Base;
|
||||||
|
}
|
||||||
|
if (MemAperture->Limit < Limit) {
|
||||||
|
MemAperture->Limit = Limit;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
Scan for all root bridges in platform.
|
||||||
|
|
||||||
|
@param[out] NumberOfRootBridges Number of root bridges detected
|
||||||
|
|
||||||
|
@retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.
|
||||||
|
**/
|
||||||
|
PCI_ROOT_BRIDGE *
|
||||||
|
ScanForRootBridges (
|
||||||
|
OUT UINTN *NumberOfRootBridges
|
||||||
|
)
|
||||||
|
{
|
||||||
|
UINTN PrimaryBus;
|
||||||
|
UINTN SubBus;
|
||||||
|
UINT8 Device;
|
||||||
|
UINT8 Function;
|
||||||
|
UINTN NumberOfDevices;
|
||||||
|
UINTN Address;
|
||||||
|
PCI_TYPE01 Pci;
|
||||||
|
UINT64 Attributes;
|
||||||
|
UINT64 Base;
|
||||||
|
UINT64 Limit;
|
||||||
|
UINT64 Value;
|
||||||
|
PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;
|
||||||
|
PCI_ROOT_BRIDGE *RootBridges;
|
||||||
|
UINTN BarOffsetEnd;
|
||||||
|
|
||||||
|
|
||||||
|
*NumberOfRootBridges = 0;
|
||||||
|
RootBridges = NULL;
|
||||||
|
|
||||||
|
//
|
||||||
|
// After scanning all the PCI devices on the PCI root bridge's primary bus,
|
||||||
|
// update the Primary Bus Number for the next PCI root bridge to be this PCI
|
||||||
|
// root bridge's subordinate bus number + 1.
|
||||||
|
//
|
||||||
|
for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {
|
||||||
|
SubBus = PrimaryBus;
|
||||||
|
Attributes = 0;
|
||||||
|
Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;
|
||||||
|
Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;
|
||||||
|
//
|
||||||
|
// Scan all the PCI devices on the primary bus of the PCI root bridge
|
||||||
|
//
|
||||||
|
for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {
|
||||||
|
|
||||||
|
for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {
|
||||||
|
|
||||||
|
//
|
||||||
|
// Compute the PCI configuration address of the PCI device to probe
|
||||||
|
//
|
||||||
|
Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Read the Vendor ID from the PCI Configuration Header
|
||||||
|
//
|
||||||
|
if (PciRead16 (Address) == MAX_UINT16) {
|
||||||
|
if (Function == 0) {
|
||||||
|
//
|
||||||
|
// If the PCI Configuration Read fails, or a PCI device does not
|
||||||
|
// exist, then skip this entire PCI device
|
||||||
|
//
|
||||||
|
break;
|
||||||
|
} else {
|
||||||
|
//
|
||||||
|
// If PCI function != 0, VendorId == 0xFFFF, we continue to search
|
||||||
|
// PCI function.
|
||||||
|
//
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Read the entire PCI Configuration Header
|
||||||
|
//
|
||||||
|
PciReadBuffer (Address, sizeof (Pci), &Pci);
|
||||||
|
|
||||||
|
//
|
||||||
|
// Increment the number of PCI device found on the primary bus of the
|
||||||
|
// PCI root bridge
|
||||||
|
//
|
||||||
|
NumberOfDevices++;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Look for devices with the VGA Palette Snoop enabled in the COMMAND
|
||||||
|
// register of the PCI Config Header
|
||||||
|
//
|
||||||
|
if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
|
||||||
|
}
|
||||||
|
|
||||||
|
BarOffsetEnd = 0;
|
||||||
|
|
||||||
|
//
|
||||||
|
// PCI-PCI Bridge
|
||||||
|
//
|
||||||
|
if (IS_PCI_BRIDGE (&Pci)) {
|
||||||
|
//
|
||||||
|
// Get the Bus range that the PPB is decoding
|
||||||
|
//
|
||||||
|
if (Pci.Bridge.SubordinateBus > SubBus) {
|
||||||
|
//
|
||||||
|
// If the suborinate bus number of the PCI-PCI bridge is greater
|
||||||
|
// than the PCI root bridge's current subordinate bus number,
|
||||||
|
// then update the PCI root bridge's subordinate bus number
|
||||||
|
//
|
||||||
|
SubBus = Pci.Bridge.SubordinateBus;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Get the I/O range that the PPB is decoding
|
||||||
|
//
|
||||||
|
Value = Pci.Bridge.IoBase & 0x0f;
|
||||||
|
Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;
|
||||||
|
Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;
|
||||||
|
if (Value == BIT0) {
|
||||||
|
Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);
|
||||||
|
Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);
|
||||||
|
}
|
||||||
|
if ((Base > 0) && (Base < Limit)) {
|
||||||
|
if (Io.Base > Base) {
|
||||||
|
Io.Base = Base;
|
||||||
|
}
|
||||||
|
if (Io.Limit < Limit) {
|
||||||
|
Io.Limit = Limit;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Get the Memory range that the PPB is decoding
|
||||||
|
//
|
||||||
|
Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;
|
||||||
|
Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;
|
||||||
|
if ((Base > 0) && (Base < Limit)) {
|
||||||
|
if (Mem.Base > Base) {
|
||||||
|
Mem.Base = Base;
|
||||||
|
}
|
||||||
|
if (Mem.Limit < Limit) {
|
||||||
|
Mem.Limit = Limit;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Get the Prefetchable Memory range that the PPB is decoding
|
||||||
|
//
|
||||||
|
Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;
|
||||||
|
Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
|
||||||
|
Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
|
||||||
|
<< 16) | 0xfffff;
|
||||||
|
MemAperture = &PMem;
|
||||||
|
if (Value == BIT0) {
|
||||||
|
Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);
|
||||||
|
Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);
|
||||||
|
MemAperture = &PMemAbove4G;
|
||||||
|
}
|
||||||
|
if ((Base > 0) && (Base < Limit)) {
|
||||||
|
if (MemAperture->Base > Base) {
|
||||||
|
MemAperture->Base = Base;
|
||||||
|
}
|
||||||
|
if (MemAperture->Limit < Limit) {
|
||||||
|
MemAperture->Limit = Limit;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// Look at the PPB Configuration for legacy decoding attributes
|
||||||
|
//
|
||||||
|
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)
|
||||||
|
== EFI_PCI_BRIDGE_CONTROL_ISA) {
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
|
||||||
|
}
|
||||||
|
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)
|
||||||
|
== EFI_PCI_BRIDGE_CONTROL_VGA) {
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
|
||||||
|
if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)
|
||||||
|
!= 0) {
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);
|
||||||
|
} else {
|
||||||
|
//
|
||||||
|
// Parse the BARs of the PCI device to get what I/O Ranges, Memory
|
||||||
|
// Ranges, and Prefetchable Memory Ranges the device is decoding
|
||||||
|
//
|
||||||
|
if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {
|
||||||
|
BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
PcatPciRootBridgeParseBars (
|
||||||
|
Pci.Hdr.Command,
|
||||||
|
PrimaryBus,
|
||||||
|
Device,
|
||||||
|
Function,
|
||||||
|
OFFSET_OF (PCI_TYPE00, Device.Bar),
|
||||||
|
BarOffsetEnd,
|
||||||
|
&Io,
|
||||||
|
&Mem, &MemAbove4G,
|
||||||
|
&PMem, &PMemAbove4G
|
||||||
|
);
|
||||||
|
|
||||||
|
//
|
||||||
|
// See if the PCI device is an IDE controller
|
||||||
|
//
|
||||||
|
if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,
|
||||||
|
PCI_CLASS_MASS_STORAGE_IDE)) {
|
||||||
|
if (Pci.Hdr.ClassCode[0] & 0x80) {
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
|
||||||
|
}
|
||||||
|
if (Pci.Hdr.ClassCode[0] & 0x01) {
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;
|
||||||
|
}
|
||||||
|
if (Pci.Hdr.ClassCode[0] & 0x04) {
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// See if the PCI device is a legacy VGA controller or
|
||||||
|
// a standard VGA controller
|
||||||
|
//
|
||||||
|
if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||
|
||||||
|
IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)
|
||||||
|
) {
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// See if the PCI Device is a PCI - ISA or PCI - EISA
|
||||||
|
// or ISA_POSITIVIE_DECODE Bridge device
|
||||||
|
//
|
||||||
|
if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {
|
||||||
|
if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||
|
||||||
|
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||
|
||||||
|
Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;
|
||||||
|
Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// If this device is not a multi function device, then skip the rest
|
||||||
|
// of this PCI device
|
||||||
|
//
|
||||||
|
if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
//
|
||||||
|
// If at least one PCI device was found on the primary bus of this PCI
|
||||||
|
// root bridge, then the PCI root bridge exists.
|
||||||
|
//
|
||||||
|
if (NumberOfDevices > 0) {
|
||||||
|
RootBridges = ReallocatePool (
|
||||||
|
(*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),
|
||||||
|
(*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),
|
||||||
|
RootBridges
|
||||||
|
);
|
||||||
|
ASSERT (RootBridges != NULL);
|
||||||
|
|
||||||
|
AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);
|
||||||
|
|
||||||
|
InitRootBridge (
|
||||||
|
Attributes, Attributes, 0,
|
||||||
|
(UINT8) PrimaryBus, (UINT8) SubBus,
|
||||||
|
&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,
|
||||||
|
&RootBridges[*NumberOfRootBridges]
|
||||||
|
);
|
||||||
|
RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;
|
||||||
|
//
|
||||||
|
// Increment the index for the next PCI Root Bridge
|
||||||
|
//
|
||||||
|
(*NumberOfRootBridges)++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return RootBridges;
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue