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UefiCpuPkg/PiSmmCpuDxeSmm: Add MemoryMapped in SetProcessorRegister() 

REGISTER_TYPE in UefiCpuPkg/Include/AcpiCpuData.h defines a MemoryMapped
enum value.  However support for the MemoryMapped enum is missing from
the implementation of SetProcessorRegister().  This patch adds support
for MemoryMapped type SetProcessorRegister().

One spin lock is added to avoid potential conflict when multiple processor
update the same memory space.

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Jeff Fan 2016-06-29 09:00:13 +08:00 committed by Michael Kinney
parent 8b9311b795
commit 6c4c15fae6
4 changed files with 27 additions and 0 deletions
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18
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
View File

@ -34,6 +34,11 @@ typedef struct {
UINTN LongJumpOffset;
} MP_ASSEMBLY_ADDRESS_MAP;
//
// Spin lock used to serialize MemoryMapped operation
//
SPIN_LOCK *mMemoryMappedLock = NULL;
/**
Get starting address and size of the rendezvous entry for APs.
Information for fixing a jump instruction in the code is also returned.
@ -284,6 +289,19 @@ SetProcessorRegister (
}
break;
//
// MemoryMapped operations
//
case MemoryMapped:
AcquireSpinLock (mMemoryMappedLock);
MmioBitFieldWrite32 (
RegisterTableEntry->Index,
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
(UINT32)RegisterTableEntry->Value
);
ReleaseSpinLock (mMemoryMappedLock);
break;
//
// Enable or disable cache
//
case CacheControl:

5
UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
View File

@ -1239,6 +1239,10 @@ InitializeSmmCpuSemaphores (
SemaphoreAddr += SemaphoreSize;
mSmmCpuSemaphores.SemaphoreGlobal.CodeAccessCheckLock
= (SPIN_LOCK *)SemaphoreAddr;
SemaphoreAddr += SemaphoreSize;
mSmmCpuSemaphores.SemaphoreGlobal.MemoryMappedLock
= (SPIN_LOCK *)SemaphoreAddr;
SemaphoreAddr = (UINTN)SemaphoreBlock + GlobalSemaphoresSize;
mSmmCpuSemaphores.SemaphoreCpu.Busy = (SPIN_LOCK *)SemaphoreAddr;
SemaphoreAddr += ProcessorCount * SemaphoreSize;
@ -1254,6 +1258,7 @@ InitializeSmmCpuSemaphores (
mPFLock = mSmmCpuSemaphores.SemaphoreGlobal.PFLock;
mConfigSmmCodeAccessCheckLock = mSmmCpuSemaphores.SemaphoreGlobal.CodeAccessCheckLock;
mMemoryMappedLock = mSmmCpuSemaphores.SemaphoreGlobal.MemoryMappedLock;
mSemaphoreSize = SemaphoreSize;
}

2
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
View File

@ -485,6 +485,8 @@ SmmRestoreCpu (
DEBUG ((EFI_D_INFO, "SmmRestoreCpu()\n"));
InitializeSpinLock (mMemoryMappedLock);
//
// See if there is enough context to resume PEI Phase
//

2
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
View File

@ -366,6 +366,7 @@ typedef struct {
volatile BOOLEAN *AllCpusInSync;
SPIN_LOCK *PFLock;
SPIN_LOCK *CodeAccessCheckLock;
SPIN_LOCK *MemoryMappedLock;
} SMM_CPU_SEMAPHORE_GLOBAL;
///
@ -413,6 +414,7 @@ extern SMM_CPU_SEMAPHORES mSmmCpuSemaphores;
extern UINTN mSemaphoreSize;
extern SPIN_LOCK *mPFLock;
extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;
extern SPIN_LOCK *mMemoryMappedLock;
/**
Create 4G PageTable in SMRAM.