mirror of https://github.com/acidanthera/audk.git
ARM Packages: Force the SEC modules to be 2K aligned for AArch64
The AArch64 Vector Table must be aligned on a 2K boundary. The FDF specification does not support 2K alignment but support 4K. A clear comment has been added to help integrator to understand why the assertion fails when porting to a new AArch64 platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin
oliviermartin
parent
9232ee5338
commit
6d0ca2577c
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/** @file
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Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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@ -131,11 +131,12 @@ InitializeExceptions (
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FiqEnabled = ArmGetFiqState ();
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ArmDisableFiq ();
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// AArch64 alignment? The Vector table must be 2k-byte aligned (bottom 11 bits zero)?
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//DEBUG ((EFI_D_ERROR, "vbar set addr: 0x%016lx\n",(UINTN)ExceptionHandlersStart));
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//ASSERT(((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
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// The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure 'Align=4K'
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// is defined into your FDF for this module.
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ASSERT (((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
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// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
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// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector
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// Base Address to point into CpuDxe code.
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ArmWriteVBar ((UINTN)ExceptionHandlersStart);
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if (FiqEnabled) {
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@ -1,7 +1,7 @@
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/** @file
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* Main file supporting the SEC Phase for Versatile Express
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*
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* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -283,9 +283,10 @@ InitializeDebugAgent (
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EFI_FFS_FILE_HEADER *FfsHeader;
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PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
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// Now we've got UART, make the check:
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// - The Vector table must be 32-byte aligned
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//Need to fix basetools ASSERT(((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
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// Now we've got UART, check the Debug Agent Vector Table
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// Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
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// 'Align=4K' is defined into your FDF for this module.
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ASSERT (((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
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ArmWriteVBar ((UINTN)DebugAgentVectorTable);
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// We use InitFlag to know if DebugAgent has been intialized from
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@ -1,13 +1,13 @@
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#
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# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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################################################################################
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@ -184,11 +184,18 @@ READ_LOCK_STATUS = TRUE
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#
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############################################################################
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[Rule.Common.SEC]
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[Rule.ARM.SEC]
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FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
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TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
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}
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# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
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# It is the reason 4K is used instead of 2K for the module alignment.
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[Rule.AARCH64.SEC]
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FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
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TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
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}
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[Rule.Common.PEI_CORE]
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FILE PEI_CORE = $(NAMED_GUID) {
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TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
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@ -1,13 +1,13 @@
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#
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# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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################################################################################
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@ -241,11 +241,18 @@ READ_LOCK_STATUS = TRUE
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#
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############################################################################
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[Rule.Common.SEC]
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[Rule.ARM.SEC]
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FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
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TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
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}
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# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
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# It is the reason 4K is used instead of 2K for the module alignment.
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[Rule.AARCH64.SEC]
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FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
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TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
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}
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[Rule.Common.PEI_CORE]
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FILE PEI_CORE = $(NAMED_GUID) {
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TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -267,7 +267,7 @@ READ_LOCK_STATUS = TRUE
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[Rule.Common.SEC]
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FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
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TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
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TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
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}
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[Rule.Common.PEI_CORE]
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2011, 2013, ARM Limited. All rights reserved.
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -240,7 +240,7 @@ READ_LOCK_STATUS = TRUE
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[Rule.Common.SEC]
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FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
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TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
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TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
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}
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[Rule.Common.PEI_CORE]
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
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# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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@ -251,7 +251,7 @@ READ_LOCK_STATUS = TRUE
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[Rule.Common.SEC]
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FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
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TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
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TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
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}
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[Rule.Common.PEI_CORE]
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@ -1,7 +1,7 @@
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/** @file
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* Main file supporting the transition to PEI Core in Normal World for Versatile Express
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*
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* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
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* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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@ -86,8 +86,9 @@ CEntryPoint (
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//
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// Write VBAR - The Exception Vector table must be aligned to its requirement
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//TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64
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//ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
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// Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
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// 'Align=4K' is defined into your FDF for this module.
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ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
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ArmWriteVBar ((UINTN)PeiVectorTable);
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//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.
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