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ARM Packages: Force the SEC modules to be 2K aligned for AArch64 

The AArch64 Vector Table must be aligned on a 2K boundary.
The FDF specification does not support 2K alignment but support 4K.

A clear comment has been added to help integrator to understand why the
assertion fails when porting to a new AArch64 platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2014-07-15 09:24:25 +00:00 committed by oliviermartin
parent 9232ee5338
commit 6d0ca2577c
8 changed files with 53 additions and 36 deletions
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11
ArmPkg/Drivers/CpuDxe/AArch64/Exception.c
View File

@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@ -131,11 +131,12 @@ InitializeExceptions (
FiqEnabled = ArmGetFiqState ();
ArmDisableFiq ();
// AArch64 alignment? The Vector table must be 2k-byte aligned (bottom 11 bits zero)?
//DEBUG ((EFI_D_ERROR, "vbar set addr: 0x%016lx\n",(UINTN)ExceptionHandlersStart));
//ASSERT(((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
// The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure 'Align=4K'
// is defined into your FDF for this module.
ASSERT (((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
// We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector
// Base Address to point into CpuDxe code.
ArmWriteVBar ((UINTN)ExceptionHandlersStart);
if (FiqEnabled) {

9
ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c
View File

@ -1,7 +1,7 @@
/** @file
* Main file supporting the SEC Phase for Versatile Express
*
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@ -283,9 +283,10 @@ InitializeDebugAgent (
EFI_FFS_FILE_HEADER *FfsHeader;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
// Now we've got UART, make the check:
// - The Vector table must be 32-byte aligned
//Need to fix basetools ASSERT(((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
// Now we've got UART, check the Debug Agent Vector Table
// Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
// 'Align=4K' is defined into your FDF for this module.
ASSERT (((UINTN)DebugAgentVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
ArmWriteVBar ((UINTN)DebugAgentVectorTable);
// We use InitFlag to know if DebugAgent has been intialized from

11
ArmPlatformPkg/ArmPlatformPkg-2ndstage.fdf
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -184,11 +184,18 @@ READ_LOCK_STATUS = TRUE
#
############################################################################
[Rule.Common.SEC]
[Rule.ARM.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
# It is the reason 4K is used instead of 2K for the module alignment.
[Rule.AARCH64.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi

11
ArmPlatformPkg/ArmPlatformPkg.fdf
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -241,11 +241,18 @@ READ_LOCK_STATUS = TRUE
#
############################################################################
[Rule.Common.SEC]
[Rule.ARM.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
# The AArch64 Vector Table requires a 2K alignment that is not supported by the FDF specification.
# It is the reason 4K is used instead of 2K for the module alignment.
[Rule.AARCH64.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi

4
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -267,7 +267,7 @@ READ_LOCK_STATUS = TRUE
[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]

4
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4-foundation.fdf
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2011, 2013, ARM Limited. All rights reserved.
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -240,7 +240,7 @@ READ_LOCK_STATUS = TRUE
[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]

4
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4.fdf
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@ -251,7 +251,7 @@ READ_LOCK_STATUS = TRUE
[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 128 $(INF_OUTPUT)/$(MODULE_NAME).efi
TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]

7
ArmPlatformPkg/PrePeiCore/PrePeiCore.c
View File

@ -1,7 +1,7 @@
/** @file
* Main file supporting the transition to PEI Core in Normal World for Versatile Express
*
* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@ -86,8 +86,9 @@ CEntryPoint (
//
// Write VBAR - The Exception Vector table must be aligned to its requirement
//TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64
//ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
// Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure
// 'Align=4K' is defined into your FDF for this module.
ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
ArmWriteVBar ((UINTN)PeiVectorTable);
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.