UefiCpuPkg/CpuCommonFeaturesLib: Remove XD enable/disable logic

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2329

XD (ExecutionDisable) feature, when turned on, allows page table
entry BIT63 set to 1 indicating the memory pointed by the page table
is disallowed to execute.
DxeIpl::CreateIdentityMappingPageTables() enables the XD when CPU
supports it.
Later DxeCore modifies the page table to set the BIT63 to protect
the stack/heap to disallow code execution in stack/heap.

UefiCpuPkg/CpuCommonFeaturesLib enables/disables the XD feature
according to PcdCpuFeaturesSetting.
When XD is disabled, GP fault is generated immediately because some
page entries have BIT63 set.

To fix this issue, this patch removes the XD feature logic from
UefiCpuPkg/CpuCommonFeaturesLib so the XD feature is only taken
care of by DxeIpl.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
This commit is contained in:
Ray Ni 2019-11-11 10:47:47 +08:00 committed by mergify[bot]
parent 49fb9f7e06
commit 6d17c9c24a
3 changed files with 1 additions and 108 deletions

View File

@ -66,17 +66,6 @@ CpuCommonFeaturesLibConstructor (
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_XD)) {
Status = RegisterCpuFeature (
"Execute Disable",
NULL,
ExecuteDisableSupport,
ExecuteDisableInitialize,
CPU_FEATURE_XD,
CPU_FEATURE_END
);
ASSERT_EFI_ERROR (Status);
}
if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) {
Status = RegisterCpuFeature (
"FastStrings",

View File

@ -4,7 +4,7 @@
# This library registers CPU features defined in Intel(R) 64 and IA-32
# Architectures Software Developer's Manual.
#
# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@ -34,7 +34,6 @@
C1e.c
ClockModulation.c
Eist.c
ExecuteDisable.c
FastStrings.c
FeatureControl.c
LimitCpuIdMaxval.c

View File

@ -1,95 +0,0 @@
/** @file
Execute Disable feature.
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#include "CpuCommonFeatures.h"
/**
Detects if Execute Disable feature supported on current processor.
@param[in] ProcessorNumber The index of the CPU executing this function.
@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
structure for the CPU executing this function.
@param[in] ConfigData A pointer to the configuration buffer returned
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
CPU_FEATURE_GET_CONFIG_DATA was not provided in
RegisterCpuFeature().
@retval TRUE Execute Disable feature is supported.
@retval FALSE Execute Disable feature is not supported.
@note This service could be called by BSP/APs.
**/
BOOLEAN
EFIAPI
ExecuteDisableSupport (
IN UINTN ProcessorNumber,
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
IN VOID *ConfigData OPTIONAL
)
{
UINT32 Eax;
CPUID_EXTENDED_CPU_SIG_EDX Edx;
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
if (Eax <= CPUID_EXTENDED_FUNCTION) {
//
// Extended CPUID functions are not supported on this processor.
//
return FALSE;
}
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32);
return (Edx.Bits.NX != 0);
}
/**
Initializes Execute Disable feature to specific state.
@param[in] ProcessorNumber The index of the CPU executing this function.
@param[in] CpuInfo A pointer to the REGISTER_CPU_FEATURE_INFORMATION
structure for the CPU executing this function.
@param[in] ConfigData A pointer to the configuration buffer returned
by CPU_FEATURE_GET_CONFIG_DATA. NULL if
CPU_FEATURE_GET_CONFIG_DATA was not provided in
RegisterCpuFeature().
@param[in] State If TRUE, then the Execute Disable feature must be enabled.
If FALSE, then the Execute Disable feature must be disabled.
@retval RETURN_SUCCESS Execute Disable feature is initialized.
@note This service could be called by BSP only.
**/
RETURN_STATUS
EFIAPI
ExecuteDisableInitialize (
IN UINTN ProcessorNumber,
IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo,
IN VOID *ConfigData, OPTIONAL
IN BOOLEAN State
)
{
//
// The scope of the MSR_IA32_EFER is core for below processor type, only program
// MSR_IA32_EFER for thread 0 in each core.
//
if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {
if (CpuInfo->ProcessorInfo.Location.Thread != 0) {
return RETURN_SUCCESS;
}
}
CPU_REGISTER_TABLE_WRITE_FIELD (
ProcessorNumber,
Msr,
MSR_IA32_EFER,
MSR_IA32_EFER_REGISTER,
Bits.NXE,
(State) ? 1 : 0
);
return RETURN_SUCCESS;
}