mirror of https://github.com/acidanthera/audk.git
MdePkg BaseLib Thunk16: Replace IA32 GAS Thunk16 with NASM version
This is a translation of Ia32/Thunk16.asm to NASM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16020 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Jordan Justen
jljusten
parent
02eef55311
commit
6dab5c8a8a
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@ -252,7 +252,7 @@
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Ia32/DisableCache.asm | INTEL
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Ia32/GccInline.c | GCC
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Ia32/Thunk16.S | GCC
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Ia32/Thunk16.nasm | GCC
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Ia32/EnableDisableInterrupts.S | GCC
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Ia32/EnablePaging64.S | GCC
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Ia32/DisablePaging32.S | GCC
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@ -0,0 +1,277 @@
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#include "BaseLibInternals.h"
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;------------------------------------------------------------------------------
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;
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; Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
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; This program and the accompanying materials
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; are licensed and made available under the terms and conditions of the BSD License
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; which accompanies this distribution. The full text of the license may be found at
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; http://opensource.org/licenses/bsd-license.php.
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;
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; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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;
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; Module Name:
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;
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; Thunk.asm
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;
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; Abstract:
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;
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; Real mode thunk
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;
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;------------------------------------------------------------------------------
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global ASM_PFX(m16Size)
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global ASM_PFX(mThunk16Attr)
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global ASM_PFX(m16Gdt)
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global ASM_PFX(m16GdtrBase)
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global ASM_PFX(mTransition)
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global ASM_PFX(m16Start)
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struc IA32_REGS
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._EDI: resd 1
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._ESI: resd 1
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._EBP: resd 1
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._ESP: resd 1
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._EBX: resd 1
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._EDX: resd 1
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._ECX: resd 1
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._EAX: resd 1
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._DS: resw 1
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._ES: resw 1
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._FS: resw 1
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._GS: resw 1
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._EFLAGS: resd 1
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._EIP: resd 1
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._CS: resw 1
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._SS: resw 1
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.size:
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endstruc
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;; .const
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SECTION .data
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;
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; These are global constant to convey information to C code.
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;
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ASM_PFX(m16Size) DW InternalAsmThunk16 - ASM_PFX(m16Start)
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ASM_PFX(mThunk16Attr) DW _ThunkAttr - ASM_PFX(m16Start)
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ASM_PFX(m16Gdt) DW _NullSegDesc - ASM_PFX(m16Start)
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ASM_PFX(m16GdtrBase) DW _16GdtrBase - ASM_PFX(m16Start)
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ASM_PFX(mTransition) DW _EntryPoint - ASM_PFX(m16Start)
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SECTION .text
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ASM_PFX(m16Start):
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SavedGdt:
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dw 0
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dd 0
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;------------------------------------------------------------------------------
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; _BackFromUserCode() takes control in real mode after 'retf' has been executed
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; by user code. It will be shadowed to somewhere in memory below 1MB.
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;------------------------------------------------------------------------------
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_BackFromUserCode:
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;
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; The order of saved registers on the stack matches the order they appears
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; in IA32_REGS structure. This facilitates wrapper function to extract them
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; into that structure.
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;
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push ss
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push cs
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DB 66h
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call @Base ; push eip
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@Base:
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pushfw ; pushfd actually
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cli ; disable interrupts
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push gs
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push fs
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push es
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push ds
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pushaw ; pushad actually
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DB 66h, 0bah ; mov edx, imm32
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_ThunkAttr: dd 0
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test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15
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jz @1
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mov eax, 15cd2401h ; mov ax, 2401h & int 15h
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cli ; disable interrupts
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jnc @2
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@1:
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test dl, THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL
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jz @2
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in al, 92h
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or al, 2
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out 92h, al ; deactivate A20M#
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@2:
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xor ax, ax ; xor eax, eax
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mov eax, ss ; mov ax, ss
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DB 67h
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lea bp, [esp + IA32_REGS.size]
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;
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; esi's in the following 2 instructions are indeed bp in 16-bit code. Fact
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; is "esi" in 32-bit addressing mode has the same encoding of "bp" in 16-
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; bit addressing mode.
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;
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mov [esi - IA32_REGS.size + IA32_REGS._ESP], bp
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mov ebx, [esi - IA32_REGS.size + IA32_REGS._EIP]
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shl ax, 4 ; shl eax, 4
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add bp, ax ; add ebp, eax
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DB 66h, 0b8h ; mov eax, imm32
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SavedCr4: DD 0
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mov cr4, eax
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DB 66h
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lgdt [cs:edi + (SavedGdt - @Base)]
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DB 66h, 0b8h ; mov eax, imm32
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SavedCr0: DD 0
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mov cr0, eax
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DB 0b8h ; mov ax, imm16
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SavedSs DW 0
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mov ss, eax
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DB 66h, 0bch ; mov esp, imm32
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SavedEsp DD 0
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DB 66h
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retf ; return to protected mode
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_EntryPoint:
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DD _ToUserCode - ASM_PFX(m16Start)
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DW 8h
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_16Idtr:
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DW (1 << 10) - 1
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DD 0
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_16Gdtr:
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DW GdtEnd - _NullSegDesc - 1
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_16GdtrBase:
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DD _NullSegDesc
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;------------------------------------------------------------------------------
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; _ToUserCode() takes control in real mode before passing control to user code.
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; It will be shadowed to somewhere in memory below 1MB.
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;------------------------------------------------------------------------------
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_ToUserCode:
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mov edx, ss
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mov ss, ecx ; set new segment selectors
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mov ds, ecx
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mov es, ecx
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mov fs, ecx
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mov gs, ecx
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mov cr0, eax ; real mode starts at next instruction
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; which (per SDM) *must* be a far JMP.
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DB 0eah
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_RealAddr: DW 0, 0
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mov cr4, ebp
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mov ss, esi ; set up 16-bit stack segment
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xchg sp, bx ; set up 16-bit stack pointer
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; mov bp, [esp + sizeof(IA32_REGS)
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DB 67h
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mov ebp, [esp + IA32_REGS.size] ; BackFromUserCode address from stack
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; mov cs:[bp + (SavedSs - _BackFromUserCode)], dx
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mov [cs:esi + (SavedSs - _BackFromUserCode)], edx
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; mov cs:[bp + (SavedEsp - _BackFromUserCode)], ebx
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DB 2eh, 66h, 89h, 9eh
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DW SavedEsp - _BackFromUserCode
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; lidt cs:[bp + (_16Idtr - _BackFromUserCode)]
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DB 2eh, 66h, 0fh, 01h, 9eh
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DW _16Idtr - _BackFromUserCode
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popaw ; popad actually
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pop ds
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pop es
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pop fs
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pop gs
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popfw ; popfd
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DB 66h ; Use 32-bit addressing for "retf" below
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retf ; transfer control to user code
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ALIGN 16
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_NullSegDesc DQ 0
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_16CsDesc:
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DW -1
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DW 0
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DB 0
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DB 9bh
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DB 8fh ; 16-bit segment, 4GB limit
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DB 0
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_16DsDesc:
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DW -1
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DW 0
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DB 0
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DB 93h
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DB 8fh ; 16-bit segment, 4GB limit
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DB 0
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GdtEnd:
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;------------------------------------------------------------------------------
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; IA32_REGISTER_SET *
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; EFIAPI
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; InternalAsmThunk16 (
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; IN IA32_REGISTER_SET *RegisterSet,
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; IN OUT VOID *Transition
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; );
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;------------------------------------------------------------------------------
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global ASM_PFX(InternalAsmThunk16)
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ASM_PFX(InternalAsmThunk16):
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push ebp
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push ebx
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push esi
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push edi
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push ds
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push es
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push fs
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push gs
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mov esi, [esp + 36] ; esi <- RegSet, the 1st parameter
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movzx edx, word [esi + IA32_REGS._SS]
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mov edi, [esi + IA32_REGS._ESP]
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add edi, - (IA32_REGS.size + 4) ; reserve stack space
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mov ebx, edi ; ebx <- stack offset
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imul eax, edx, 16 ; eax <- edx * 16
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push IA32_REGS.size / 4
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add edi, eax ; edi <- linear address of 16-bit stack
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pop ecx
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rep movsd ; copy RegSet
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mov eax, [esp + 40] ; eax <- address of transition code
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mov esi, edx ; esi <- 16-bit stack segment
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lea edx, [eax + (SavedCr0 - ASM_PFX(m16Start))]
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mov ecx, eax
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and ecx, 0fh
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shl eax, 12
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lea ecx, [ecx + (_BackFromUserCode - ASM_PFX(m16Start))]
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mov ax, cx
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stosd ; [edi] <- return address of user code
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add eax, _RealAddr + 4 - _BackFromUserCode
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mov [edx + (_RealAddr - SavedCr0)], eax
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sgdt [edx + (SavedGdt - SavedCr0)]
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sidt [esp + 36] ; save IDT stack in argument space
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mov eax, cr0
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mov [edx], eax ; save CR0 in SavedCr0
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and eax, 7ffffffeh ; clear PE, PG bits
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mov ebp, cr4
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mov [edx + (SavedCr4 - SavedCr0)], ebp
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and ebp, ~30h ; clear PAE, PSE bits
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push 10h
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pop ecx ; ecx <- selector for data segments
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lgdt [edx + (_16Gdtr - SavedCr0)]
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pushfd ; Save df/if indeed
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call dword far [edx + (_EntryPoint - SavedCr0)]
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popfd
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lidt [esp + 36] ; restore protected mode IDTR
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lea eax, [ebp - IA32_REGS.size] ; eax <- the address of IA32_REGS
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pop gs
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pop fs
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pop es
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pop ds
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pop edi
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pop esi
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pop ebx
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pop ebp
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ret
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